Design and Analysis of CMOS Analog Circuit in Systematic Method on 130nm

The trend of scaling down mixed or analog signal integrated circuit (IC) technology allows digital circuits to fully embrace reduced feature sizes, but it significantly limits the performance of analogue circuits. This places a great expectation on analogue circuits to provide equivalent and acceptable performance with CMOS technology, which has a higher threshold voltage than other technologies. This paper investigated the different between conventional method and Systematic method. As conventional design method applied on long channel MOSFET devices produce inaccurate results in strong inversion regions also, failed to describe the behavior of transistors in moderate and weak inversion level, it allows the designer to meet the desired OTA specifications at all levels. It succeeded in exploring the behavior of transistors at all levels of operating points. The complete design process is illustrated on a simple analog block called operational Transconductance amplifier. The paper also provides a result comparison with where design is carried on 180nm process with different topology. For systematic process need to develop design charts for both NMOS and PMOS in cadence or SPICE. Based on design specifications design topology is fixed. Thus, OTA is designed under the UMC 130nm technology process and verified in cadence.