An Energy Efficient and Fast Hybrid Full Adder Circuit

This paper presents a new design of a 1-bit full adder featuring a hybrid complementary-metal-oxide-semicondoctor (CMOS) design style. The quest to achieve good drivability, noise-robustness and low-energy operation for deep submicron led to the exploration of the hybrid-CMOS design style. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. The proposed cell using HSPICE as a framework is implemented with 16-nm FinFET technology. This gives the designer a greater degree of design freedom to target multiple applications, thus significantly reducing design efforts. In this work, a novel design of a full adder is proposed. This full adder is implemented using an XOR–XNOR circuit simultaneously generating the XOR-XNOR full-swing outputs. Proposed design reports 8.08% to 69.5% improvement in the power delay product (PDP) when compared to existing designs.