Architectural Designs and Performance Analysis of Adiabatic-based 6T, 9T, and 12T SRAM Cells

Many applications use SRAM as the core memory architecture, which necessitates the development of various SRAM cell architectures. A few design methods of SRAM cells use various low-power techniques, but adiabatic logic, such as reversible gates, proves its performance improvement by providing zero heat dissipation. In this paper, the design of each 6T, 9T, and 12T SRAM cell using Feynman and Toffoli gates is presented. While comparing the results of both Feynman and contemporary CMOS based SRAM designs, it is observed that the critical path delay is reduced and speed improvement is raised by 62.7%, 82.3%, and 69.2%, respectively. It is also observed from the results that the maximum operating current Imax is less in Toffoli based SRAM designs, and the reduction advantage is 99.5% and 40% in 9T and 12T cells, respectively. Furthermore, the area reduction advantage is observed in Feynman-based SRAMs at 17%, 63.5%, and 10.8%, respectively, and is much more comparable to CMOS-based SRAMs.