A Compact W-Band Power Amplifier With a Peak PAE of 21.1% in 65-nm CMOS Technology

This letter presents a high-gain and high-efficiency
${W}$
-band power amplifier (PA) fabricated in a 65-nm CMOS technology. By elaborating the matching loss (ML) of the conventional transformer-based interstage matching network, an inductor-enhanced high-
$k$
(IEH-
${k}$
) transformer-based interstage matching network is proposed to reduce the ML and, hence, promote the gain and power efficiency of the PA with a small chip area cost. The proposed network improves the ML by 1.1 dB and is demonstrated in a single-path three-stage PA. The measurement results exhibit that the PA achieves a peak gain of 20.0 dB with a 3-dB bandwidth from 92.5 to 98.5 GHz. The saturated output power (
${P} _{\textrm {sat}}$
), output-referred 1-dB compression point (OP
$_{\textrm {1 dB}}$
), and peak power-added efficiency (PAEmax) are 13.0 dBm, 12.8 dBm, and 21.1% at 98 GHz, respectively.