Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks

This article proposes a fractional wavelet filter (FrWF)-based 2-D discrete wavelet transform (DWT) architecture for the 9/7 Cohen–Daubechies–Feauveau (CDF) filter employed at the wireless visual sensor nodes (VSNs) for preprocessing of images. Two very large-scale integration (VLSI) architectures of an FrWF-based 2-D DWT for a 9/7 CDF filter are proposed here. The first design employs raster scanning order as the data access scheme and is termed horizontal-FrWF (H-FrWF), whereas the second design employs vertical scanning order as the data access scheme and is termed vertical-FrWF (V-FrWF). The proposed architectures and best of the existing 2-D DWT architectures are modeled in Verilog Hardware Description Language (HDL), simulated using Vivado 2019.1, and synthesized using the gpdk090 library by Cadence Genus Synthesis Solution. The implementation results reveal that both the proposed architectures are memory-efficient and significantly improve area and power compared to state-of-the-art designs. The proposed V-FrWF architecture has constant latency, and the dependency of the memory requirement for FrWF computation on the resolution of the image is eliminated. Moreover, the proposed architectures are capable of computing the 2-D DWT of high-resolution (HR) images with high image quality, making them expedient for wireless sensor networks (WSNs).