Reliability of Atomic-Layer-Deposited Gate-All-Around In2O3 Nano-Ribbon Transistors with Ultra-High Drain Currents

In this work, we systematically investigate the reliability of atomic-layer-deposited (ALD) gate-all-around (GAA) single-channel In
2
O
3
nano-ribbon field-effect transistors (FETs) with 5 nm HfO
2
gate dielectric and a maximum on-state current (I
ON
) approaching 20 mA/μm at drain voltage (V
DS
) of 1.7 V. A channel length (L
ch
) and channel width (W
ch
) independent positive threshold voltage (V
T
) shift under negative gate bias stress (NBS) and a negative V
T
shift under positive gate bias stress (PBS) are observed universally in all GAA In
2
O
3
FETs, which is opposite to bias instability of the conventional Si CMOS and IGZO thin film transistors (TFTs). This unusual behavior can be simply explained by the concept of the trap neutral level (TNL) which is deeply aligned inside the In
2
O
3
conduction band and the generation of donor-and acceptor-like traps in different gate bias stress conditions. In addition, other reliability issues including stress and recovery, gate bias dependence and temperature dependence are also studied. This comprehensive reliability analysis establishes ALD In
2
O
3
as a competitive channel material of the back-end-of-line (BEOL) compatible FETs for 3D monolithic integration into next generation ICs.