Highly reliable STT-MRAM adopting advanced MTJs with controlled domain wall pinning

We demonstrate highly reliable STT-MRAM whose array-level write error has been eliminated by lowering the density of domain wall pinning sites in the MTJs. The core part of investigation includes the identification and quantification of domain wall pinning sites, characterization and modeling of the pinning sites, and correlation of the density of pinning sites with array-level write error rate. The experimental results show that domain wall pinning is geometrically localized and reproduced upon the repeated writing cycles. By controlling the domain wall pinning, we obtain high-density MTJ array having superior reliability without notable trailing bits of write fail.