5 GHz Phase-Locked Loop With a Phase-Adjusting Function

The design of a 5 GHz phase-locked loop (PLL) with a phase-adjusting function is presented. The voltage-controlled delay line (VCDL) is proposed to adjust the feedback signal phase by an externally controlled voltage. The output phase difference of multi-PLLs can be shifted from 0° to 98.6°, when the propagation delay of VCDL is 0.41 and 4.75 ns, respectively. The proposed PLL was fabricated in TSMC 0.18-
$\mu \text{m}$
CMOS process and supplied at 1.8 V with a power dissipation of 16.38 mW. The locking time is less than
$2 ~\mu \text{s}$
under the different controlled-voltage ranges of VCDL.