PCB Design Parameters of Reducing Copper Trace Crack under Temperature Cycle Test

During the board level TCT (temperature cycle testing), the dominant failure mode is solder bulk fatigue. However, in some specific cases, track crack was found occasionally in the substrate or PCB (printed circuit board) depending on the assembly capabilities and structural parameter variations. There are several reasons that result in trace damage such as oxidation in copper or micro-voids propagation during thermal treatments, and stress concentration at critical points. This study mainly focuses on the mechanical behavior of structures, so FE (finite element) model is used to analyze the weakness of the detailed geometry on PCB trace and then provides some optimized design options. The targeted traces are built at the location under chip edge. Investigations include choosing the better size of width and thickness, minor shifting the die location in package, and rotating the trace angle properly. Although SJR (solder joint reliability) is one of the indexes for product specification, a good understanding of failure risk will help to prolong the lifetime cycle when there is some room to adjust the board layout.