Design of Software-Hardware Collaborative Graph Computing Accelerator Based on RISC-V

The irregularities in the execution process of graph computing applications lead to the existing common architecture facing huge challenges in computing, accessing and other aspects. Dedicated accelerators can improve computing performance, but it is difficult to effectively cope with characteristics such as poor locality of graph data. Combining the respective advantages of a common architecture and a dedicated accelerator can effectively alleviate the challenges of graph computing today. In this paper, based on RISC-V oriented connected component and minimum spanning tree algorithm, a software and hardware cooperative graph computing accelerator and a special co-processor instruction are designed, and an instruction compilation environment and acceleration function library are established. Based on the MCU 200T platform, this paper uses p2pGnutella05, wikiVote, Facebook_combined and DaysALL data sets to prototype the accelerator. The results show that the accelerator designed in this paper reduces the resources by 75.6% compared with the mainstream accelerator HitGraph, and reduces the resources by 97.5% compared with the accelerator designed with high parallelization. The power consumption of the connected component algorithm accelerator decreased by 92.3%, the throughput increased by $1.65 \times$, and the power efficiency increased by $16.27 \times$; the power consumption of the minimum spanning tree algorithm accelerator decreased by 82.1%, the throughput increased by $1.44 \times$, and the power efficiency increased by $8.16 \times$.