A 9-bit 500-MS/s 2-then-1b/cycle SAR ADC with Dynamic Background Offset Calibration Technique

This paper presents a low power asynchronous 9-bit 500-MS/s 2-then-1b/cycle successive approximation register (SAR) ADC in 40-nm CMOS technology. The proposed efficient ADC shows good performance against offset mismatch of the comparator array by background calibration technique. The operation of the proposed background calibration module does not depend on the input signal distribution by quantizing the same residue signal in the last 1b/cycle phase. This module which is turned on dynamically without extra comparison phase can reduce conversion time. A majority vote logic is also introduced to improve the effective number of bits (ENOB) of the ADC. The calibration enhances SFDR from 61.63 dB to 68.7 dB, ENOB from 7.57 bits to 8.79 bits, SNDR from 47.38 dB to 54.7 dB for a near-Nyquist input. The proposed SAR ADC consumes 2.11mW under 1.1V supply with Walden Figure of merit (FOM) of 9.27 fJ/conversion-step.