A High Efficiency Memristor Array Simulation Model for Memristive Neuromorphic Chip Design

In the design of memristive neuromorphic chip, the memristor array and its peripheral circuits need to be simulated to confirm the correctness of the circuit design. However, almost all existing memristor models are designed for a single device. When array simulation is carried out, a large amount of memristor models need to be instantiated to form an array, which usually consumes huge simulation time and memory. In order to improve the efficiency of circuit simulation, this paper proposes a memristor array simulation model for the design of memristive neuromorphic chips. The model simulates the largesize memristor array by combining the small-size memristor array with the lumped parasitic parameter models, which can accurately simulate the change of the resistance states of the operated devices and the action of the driving circuits, and also reduce the time and memory required for simulation. The experimental results show that, to simulate a 64×64 memristor array, this method can reduce simulation time and memory by 99.21% and 43.15% respectively, than those of instantiating all memristors.