Design of Hybrid Memory Built in Self Test using Linear Feedback Shift Registers

Built in self-test (BIS T) modules are essential devices in various application, which includes microprocessors, microcontroller, multi-core system, and multi-processor systems. The conventional BIS T modules are failed to solve the pro blems presented in various memories, which are affected by the stuck at faults. Therefore, this work is focused on implementation of a Hybrid Memory Logic (HML)-BIS T, which is used to detect and correct the errors presented in the memory elements. Initially, linear feedback shift register (LFS R) modules introduced for generating the random test patterns for write address, read address and write data. Here, activity factor is used to generate the non-repeated random numbers from LFSR Then, the data stored in memory are compared with original source data using space comparator. Finally, the BIS T module corrects the memory for various test cases. The simulations revealed that the proposed HML-BIS T method resulted in better area, delay, power performance as compared to conventional MBIST [16], PSRG-BIST [15], and FT-BIST [14] approaches.