FPGA Implementation of PRESENT Block Cypher with Optimised Substitution Box

Conventional cryptographic techniques such as Advanced Encryption Standard (AES) being resource intensive are not feasible for low-end Internet of Things (IoT) devices. As such, several lightweight crypto primitives have been designed to offer an optimum level of security along with reduced resource utilisation. Also, because of the trade-offs between different metrics, lightweight cryptography often targets a specific parameter, making it a good fit for a particular field of IoT application. This paper aims to reduce the hardware footprint of the PRESENT block cypher with the area-efficient hardware design of Substitution-Box, which is the most resource-consuming part of the PRESENT cypher. The proposed hardware design for S-Box is implemented in the state-of-the-art architectures reported in the literature. The designs are implemented on the FPGAs to assess resource consumption and performance. The original designs and their implementation with the proposed hardware for S-Box have been compared in terms of resource consumption, maximum achievable throughput, and throughput per slice. The results indicate a 13.67% improvement in resource consumption by adopting the proposed S-Box in the architecture. Moreover, throughput has been increased for certain PRESENT architectures, thus enhancing their overall performance.