FPGA Implementation of Lattice-Wave Half-Order Digital Integrator using Radix-$2^{r}$ Digit Recoding

This paper presents the FPGA implementation of half-order digital integrator configured in lattice wave digital structure. The optimal lattice wave coefficients for 3
^rd
and 5
^th
structure are obtained using the Driving Training-Based Opti-mization(DTBO) algorithm to approximate integration operator. The Simulink model of the resulting lattice wave structure shows less susceptibility compared to the traditional IIR realization for finite precision data representation. The radix
$-2^{r}$
encoding based multiplication is utilized for the efficient multiplier-less implementation of the suggested lattice wave design on FPGA using Xilinx system generator for DSP.