A Selective Bit Dropping and Encoding Co-Strategy in Image Processing for Low-Power Design in DRAM and SRAM

A novel and efficient way of image processing is proposed in this paper, which fully exploits the features of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) as well as the human visual system. The proposed strategy first approximates and encodes the image to effectively reduce the number of bit-‘1’ in the original pixel data, then the processed data is pushed into the off-chip DRAM, and later written into the on-chip SRAM for further computation. Since the storage power consumption of DRAM is proportional to the number of bit-‘1’, while the write power consumption of SRAM is linear relative to the switch probability and the square of the supply voltage, fewer bits-‘1’ in the processed pixel data will decrease the power consumption of DRAM and SRAM, yet accompanied by negligible influence on output quality as our proposed method has the advantages of both approximate computation and error compensation. Thus, a tradeoff is finally achieved between storage power consumption and output quality. In the experimental simulations, 39.8% power reduction for DRAM and 25.9% write power reduction for SRAM have been achieved. Regarding output quality, Discrete Cosine Transform (DCT), quantization, inverse quantization and inverse DCT (IDCT) are employed to process the approximated data. The simulations shows average 3.36 dB losses in Peak-Signal-Noise-Ratio (PSNR). Based on this strategy, an approach of priority-based reduction in supply voltage for insignificant pixel data is introduced to achieve further reduction in power consumption for SRAM. Undoubtedly, a lower supply voltage will increase the probability of read error from SRAM. However, with our proposed approximate coding strategy, the output quality is barely impacted by the lower supply voltage.