1-V 87-nW CMOS Rail-to-Rail Amplifier Using an Optimization methodology

The design of analog circuits is widely regarded as a time-consuming task because of the strong dependence of analog performance on transistor and passive dimensions. Through various automation approaches, significant effort has been made to shorten the front-end design cycles of analog circuits over the last two decades. By proposing an effective simulation-based methodology, the objective is to highlight the remaining challenges as well as the most relevant research directions to explore. A 1 V rail-to-rail amplifier with low power operation is proposed and optimized with the proposed optimization framework. Using CMOS $0.18~\mu \mathrm{m}$ technology with a supply voltage of 1 V, our optimization results showed a DC gain of 78.14 dB, a dissipation power of 87 nW, a unity gain bandwidth of 4.65 kHz, and a slew rate of 1 V/ms at 10 pF load capacitance.