Low power CMOS bridge Rectenna

In this research work, a CMOS full wave bridge rectifier is designed with different topologies. These topologies are compared to optimize the efficiency at a low power input level. The considered key optimization parameters are transistor size, load resistor and voltage holder capacity. The main objective of this study is the bridge topology itself, operating on 2.45 GHz Wi-Fi frequency and low input power levels below 0 dBm. Two scenarios of −5 dBm and −26 dBm input power are tested and the best Power Conversion Efficiency (PCE) are respectively 69% and 43.6%. In order to achieve considerable power level at the rectifier input, a primary analysis has been conducted for an array antenna of four circular elements achieving all together a Gain = 11.4dB and S11 = −13.03dB.