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Changgang Li - IEEE Xplore Author Profile

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Author details

Changgang Li

Also published under: Chang-gang Li

Publications

76

Citations

494

Publications by Year

20092025

Co-Authors:

Shibin BaiNavin BhattJiawen CaoYongji CaoYanzhao Chang

Show All Co-Authors (162)

Changgang Li

Also published under: Chang-gang Li

Affiliation

Key Laboratory of Power System Intelligent Dispatch and Control of the Ministry of Education

Shandong University

Jinan, China

Publication Topics

Power System,
Power Grid,
Wind Power,
Wind Farm,
Input Features,
Transient Stability,
Wind Turbine,
Bus Voltage,
Deep Learning,
Dynamics Simulations,
Long Short-term Memory,
Neural Network

Biography

Changgang Li (M’15) received the B.E. and Ph.D. degrees in electrical engineering from Shandong University, Jinan, China, in 2006 and 2012, respectively. He was a Research Scholar with the School of Electrical Engineering and Computer Science, The University of Tennessee, Knoxville, TN, USA, from 2012 to 2014. He is currently an Associate Research Fellow with the School of Electrical Engineering, Shandong University. His research interest includes power system operation and control.(Based on document published on 26 September 2019).

Publications

76

Citations

494

Publications by Year

20092025

Co-Authors:

Shibin Bai
Navin Bhatt
Jiawen Cao
Yongji Cao
Yanzhao Chang

Show All Co-Authors (162)

Author's Published Works

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Showing 1-7 of 7 results

Conferences (6)

Journals (1)

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Qing Jin(7)
Kaiyuan Yang(5)
Yanzhi Wang(5)
Zhiyu Chen(4)
Zhanghao Yu(3)
Rice University, Houston, TX(2)
Northeastern University, Boston, MA(2)
Xi’an Jiaotong University, Xi’an, China(1)
ByteDance Inc.(1)
College of William and Mary(1)
2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)(2)
2019 IEEE Custom Integrated Circuits Conference (CICC)(1)
2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)(1)
2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)(1)
2022 IEEE Custom Integrated Circuits Conference (CICC)(1)
IEEE(7)
Nashville, TN, USA(2)
Austin, TX, USA(1)
Boston, MA, USA(1)
Newport Beach, CA, USA(1)
Seattle, WA, USA(1)
Energy Efficiency(3)
Inference Accuracy(3)
Neural Architecture Search(3)
Analog Computing(2)
Bottom Plate(2)

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DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization

Zhiyu Chen;Qing Jin;Zhanghao Yu;Yanzhi Wang;Kaiyuan Yang

2022 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2022 | Conference Paper |

Cited by: Papers (11)

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Process-In-Memory (PIM) is a promising solution to alleviating the memory-wall bottleneck in memory-intensive applications like CNNs. Recent demonstrations of SRAM-based PIM designs, particularly those computing in the charge domain [1]–[5], have greatly improved the linearity of analog multiply-and-add computations (MAC) and quantization, and their robustness to process variations, making their i...Show More

DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization

Zhiyu Chen;Qing Jin;Zhanghao Yu;Yanzhi Wang;Kaiyuan Yang

2022 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2022 | Conference Paper |

Teachers Do More Than Teach: Compressing Image-to-Image Models

Qing Jin;Jian Ren;Oliver J. Woodford;Jiazhuo Wang;Geng Yuan;Yanzhi Wang;Sergey Tulyakov

2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2021 | Conference Paper |

Cited by: Papers (36)

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Generative Adversarial Networks (GANs) have achieved huge success in generating high-fidelity images, however, they suffer from low efficiency due to tremendous computational cost and bulky memory usage. Recent efforts on compression GANs show noticeable progress in obtaining smaller generators by sacrificing image quality or involving a time-consuming searching process. In this work, we aim to ad...Show More

Teachers Do More Than Teach: Compressing Image-to-Image Models

Qing Jin;Jian Ren;Oliver J. Woodford;Jiazhuo Wang;Geng Yuan;Yanzhi Wang;Sergey Tulyakov

2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2021 | Conference Paper |

NPAS: A Compiler-aware Framework of Unified Network Pruning and Architecture Search for Beyond Real-Time Mobile Acceleration

Zhengang Li;Geng Yuan;Wei Niu;Pu Zhao;Yanyu Li;Yuxuan Cai;Xuan Shen;Zheng Zhan;Zhenglun Kong;Qing Jin;Zhiyu Chen;Sijia Liu;Kaiyuan Yang;Bin Ren;Yanzhi Wang;Xue Lin

2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2021 | Conference Paper |

Cited by: Papers (15)

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With the increasing demand to efficiently deploy DNNs on mobile edge devices, it becomes much more important to reduce unnecessary computation and increase the execution speed. Prior methods towards this goal, including model compression and network architecture search (NAS), are largely performed independently, and do not fully consider compiler-level optimizations which is a must-do for mobile a...Show More

NPAS: A Compiler-aware Framework of Unified Network Pruning and Architecture Search for Beyond Real-Time Mobile Acceleration

Zhengang Li;Geng Yuan;Wei Niu;Pu Zhao;Yanyu Li;Yuxuan Cai;Xuan Shen;Zheng Zhan;Zhenglun Kong;Qing Jin;Zhiyu Chen;Sijia Liu;Kaiyuan Yang;Bin Ren;Yanzhi Wang;Xue Lin

2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2021 | Conference Paper |

MC2-RAM: An In-8T-SRAM Computing Macro Featuring Multi-Bit Charge-Domain Computing and ADC-Reduction Weight Encoding

Zhiyu Chen;Qing Jin;Jingyu Wang;Yanzhi Wang;Kaiyuan Yang

2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2021 | Conference Paper |

Cited by: Papers (12)

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In-memory computing (IMC) is a promising hardware architecture to circumvent the memory walls in data-intensive applications, like deep learning. Among various memory technologies, static random-access memory (SRAM) is promising thanks to its high computing accuracy, reliability, and scalability to advanced technology nodes. This paper presents a novel multi-bit capacitive convolution in-SRAM comp...Show More

MC2-RAM: An In-8T-SRAM Computing Macro Featuring Multi-Bit Charge-Domain Computing and ADC-Reduction Weight Encoding

Zhiyu Chen;Qing Jin;Jingyu Wang;Yanzhi Wang;Kaiyuan Yang

2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2021 | Conference Paper |

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

Zhiyu Chen;Zhanghao Yu;Qing Jin;Yan He;Jingyu Wang;Sheng Lin;Dai Li;Yanzhi Wang;Kaiyuan Yang

IEEE Journal of Solid-State Circuits

Year: 2021 | Volume: 56, Issue: 6 | Journal Article |

Cited by: Papers (81)

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A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adop...Show More

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

Zhiyu Chen;Zhanghao Yu;Qing Jin;Yan He;Jingyu Wang;Sheng Lin;Dai Li;Yanzhi Wang;Kaiyuan Yang

IEEE Journal of Solid-State Circuits

Year: 2021 | Volume: 56, Issue: 6 | Journal Article |

AdaBits: Neural Network Quantization With Adaptive Bit-Widths

Qing Jin;Linjie Yang;Zhenyu Liao

2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2020 | Conference Paper |

Cited by: Papers (81)

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Deep neural networks with adaptive configurations have gained increasing attention due to the instant and flexible deployment of these models on platforms with different resource budgets. In this paper, we investigate a novel option to achieve this goal by enabling adaptive bit-widths of weights and activations in the model. We first examine the benefits and challenges of training quantized model ...Show More

AdaBits: Neural Network Quantization With Adaptive Bit-Widths

Qing Jin;Linjie Yang;Zhenyu Liao

2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)

Year: 2020 | Conference Paper |

A 0.84pJ/cycle Wheatstone Bridge Based CMOS RC Oscillator with Reconfigurable Frequencies

Peiyu Chen;Dai Li;Zhanghao Yu;Qing Jin;Kaiyuan Yang

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

Cited by: Papers (16)

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A low-power CMOS RC relaxation oscillator supporting reconfigurable frequencies is presented for timekeeping in low-power Internet of Things (IoT) devices. The oscillator employs a Wheatstone Bridge (WB) scheme to relax the constraint between reference current and reference resistance existing in prior arts. In addition, adjusting the resistor ratios in WB supports reconfigurable frequencies and a...Show More

A 0.84pJ/cycle Wheatstone Bridge Based CMOS RC Oscillator with Reconfigurable Frequencies

Peiyu Chen;Dai Li;Zhanghao Yu;Qing Jin;Kaiyuan Yang

2019 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2019 | Conference Paper |

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