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Vincenzo Ambriola - IEEE Xplore Author Profile

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Vincenzo Ambriola

Also published under: V. Ambriola

Publications

9

Citations

88

Publications by Year

19852021

Co-Authors:

R. BisianiP. CiancariniV. GervasiF. GiannottiBarbara Guidi

Show All Co-Authors (12)

Vincenzo Ambriola

Also published under: V. Ambriola

Affiliation

Department of Computer Science, University of Pisa, Italy

Publication Topics

Flow Data,
Natural Language,
Set Of Requirements,
Set Of Rules,
Active Users,
Algorithm In Order,
Analysis Of Users,
Analysis System,
Content Categories,
Drafting Process,
Ego Network,
Form Of Representation

Publications

9

Citations

88

Publications by Year

19852021

Co-Authors:

R. Bisiani
P. Ciancarini
V. Gervasi
F. Giannotti
Barbara Guidi

Show All Co-Authors (12)

Author's Published Works

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Showing 1-4 of 4 results

Conferences (4)

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Gengsheng Chen(3)
Xiaofang Zhou(2)
Jiyuan Bai(2)
Zixiang Chen(1)
Zhenyin Zhang(1)
School of Microelectronics, Fudan University, Shanghai, China(3)
Jiashan Fudan Institute, Jiaxing, Zhejiang Province, China(3)
National Key Laboratory of Science and Technology on Communications, University of Electronic Science and Technology, Chengdu, Sichuan, China(1)
2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)(3)
23rd IEEE International SOC Conference(1)
IEEE(4)
Zhuhai, China(3)
Las Vegas, NV, USA(1)
2D Images(1)
3D Joint(1)
3D Mesh(1)
3D Method(1)
3D Pose(1)

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A Unified Verification Scheme for the Acceleration of RISC-V Processor Design

Zixiang Chen;Jiyuan Bai;Yueru Yu;Gengsheng Chen;Xiaofang Zhou

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

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This paper presents a unified verification scheme for design and verification of large-scale complex digital systems. The new scheme integrates the software simulation environment and the hardware accelerating resources to undertake a unified and automated verification of large-scale digital circuit systems, encompassing test generation, result comparison, and coverage analysis. The non-synthesiza...Show More

A Unified Verification Scheme for the Acceleration of RISC-V Processor Design

Zixiang Chen;Jiyuan Bai;Yueru Yu;Gengsheng Chen;Xiaofang Zhou

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

Low Power Processor for IoT Device

Jincheng Li;Jiyuan Bai;Zelin Wang;GengSheng Chen;Xiaofang Zhou

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

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Internet-of-Things(IoT) devices demand features such as long runtime, low heat dissipation and high reliability, as collecting and transmitting data under limited power supply. Therefore, there is a pressing demands for low power consumption and multi operation modes. Based on above requirements, we proposes ZCLP, a processor deploys clock gating and sleep mode. Prototypes are fabricated under TSM...Show More

Low Power Processor for IoT Device

Jincheng Li;Jiyuan Bai;Zelin Wang;GengSheng Chen;Xiaofang Zhou

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

SST: Simplified Space-Time Transformer Based on Time-Assisted Spatial MSA for 3D Human Pose Estimation

Sheng Lu;Qiyun Dong;Zhenyin Zhang;Gengsheng Chen;Yinna Zhu;Wei Xu

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

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Depth ambiguity in 2D human joint estimation is a persistent issue for 2D-3D human pose estimation networks. To cope with this challenge, temporal dimensions are adopted in existing models, however, none of them are able to fully utilize the information embedded in the input data. In this paper, we present a Time-assisted Spatial (TaS) MSA & Simplified Space-Time Transformer (SST) to better captur...Show More

SST: Simplified Space-Time Transformer Based on Time-Assisted Spatial MSA for 3D Human Pose Estimation

Sheng Lu;Qiyun Dong;Zhenyin Zhang;Gengsheng Chen;Yinna Zhu;Wei Xu

2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

Year: 2024 | Conference Paper |

Energy and delay-aware mapping for real-time digital processing system on network on chip platforms

Yiou Chen;Jianhao Hu;Gengsheng Chen;Xiang Ling

23rd IEEE International SOC Conference

Year: 2010 | Conference Paper |

Cited by: Papers (2)

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The mapping algorithm is one of the most important topics for Network on chip design. This paper proposes a new mapping algorithm, which uses an optimized energy model. In addition, we adopt a multiple-to-multiple mapping scheme to enhance concurrency and increase efficiency. The proposed approach uses NSGA-II to achieve the global optimal solutions for NoC platforms. The simulation results prove ...Show More

Energy and delay-aware mapping for real-time digital processing system on network on chip platforms

Yiou Chen;Jianhao Hu;Gengsheng Chen;Xiang Ling

23rd IEEE International SOC Conference

Year: 2010 | Conference Paper |

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