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Chih-Hung Hsiao - IEEE Xplore Author Profile

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After the increase of pollution caused by vehicle congestion, new approaches to reduce pollution have emerged. Although regular visits to technical inspection centers and car repair center can be helpful, a new approach is to achieve effective integration between mobile applications and vehicles. This integration can be achieved using the ELM327 interface, which provides data such as speed, fuel c...Show More
Vehicle speed is known as one of the most important parameters in the various goals for driving. Although the most critical goal of driving is safety, each driver can consider another secondary goal, such as reducing travel time, economical driving, green driving, passenger comfort, etc. In this paper, we propose a smartphone-based application that utilizes the cloud/fog computing service infrastr...Show More
Nowadays, the costs of car accidents have a catastrophic impact on human societies. To this end, a number of research have been conducted in order to design systems that are able to detect driving violations. Similarly, the present study was conducted to propose an approach that is able to detect and classify the driver’s behavior into two categories, which are labeled as traffic offender and non-...Show More
One-class classification (OCC) poses as an essential component in many machine learning and computer vision applications, including novelty, anomaly, and outlier detection systems. With a known definition for a target or normal set of data, one-class classifiers can determine if any given new sample spans within the distribution of the target class. Solving for this task in a general setting is pa...Show More
Automatic human activity recognition is an integral part of any interactive application involving humans (e.g., human–robot interaction systems). One of the main challenges for activity recognition is the diversity in the way individuals often perform activities. Furthermore, changes in any of the environment factors (i.e., illumination, complex background, human body shapes, viewpoint, etc.) inte...Show More
Information technology (IT) and telecommunication age require novel systems in electronic payments with the new approach of the Internet of Everything(IoE). One of the most widely used categories in various countries is Near-Field Communication (NFC) technology, and as all people use cell-phones, it is necessary to implement electronic payment methods with cell-phones in Iran. Evaluation of the ac...Show More
Real-time health monitoring systems play a critical role in preventing heart disease by processing vital sign monitoring data. The internet of things will enhance the entire health care service-delivery and can lead to reducing the immediate risk in real-time. Fog assisted health-care IoT system and Edge computing technology are an emerging paradigm that reducing emergency response time and enhanc...Show More
In recent years, deep learning-based networks have achieved state-of-the-art performance in medical image segmentation. Among the existing networks, U-Net has been successfully applied on medical image segmentation. In this paper, we propose an extension of U-Net, Bi-directional ConvLSTM U-Net with Densely connected convolutions (BCDU-Net), for medical image segmentation, in which we take full adv...Show More
Novelty detection is the process of identifying the observation(s) that differ in some respect from the training observations (the target class). In reality, the novelty class is often absent during training, poorly sampled or not well defined. Therefore, one-class classifiers can efficiently model such problems. However, due to the unavailability of data from the novelty class, training an end-to...Show More
Future dark silicon chip-multiprocessors (CMPs) consist of many cores and uncores where only a few of them can be simultaneously powered on or utilized within the peak power. In this paper, we present a run-time convex optimization to reconfigure hybrid cache hierarchy and 3D NoC based CMP to minimize the power consumption and improves chip performance. The proposed approach dynamically estimate t...Show More
The 3D design of SRAM LLCs has made the thermal problem, even more, sever and therefore incurs more leakage energy consumption compared to conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose a runtime cache architecture called NIZCache. The core idea of NIZCache is to use the non-uniform distribution of the accesses, invalid lines, and zero-value lines ...Show More
MicroRNAs (miRNAs) are short non-coding RNAs which bind to mRNAs and regulate their expression. MiRNAs have been found to be associated with initiation and progression of many complex diseases. Investigating miRNAs and their targets can thus help develop new therapies by designing anti-miRNA oligonucleotides. While existing computational approaches can predict miRNA targets, these predictions have...Show More
This paper presents an analytical model for future high performance computing architecture design exploration. We proposed a convex optimization model and applied it as a run-time solution for 3D stacked cache which is designed with volatile STT-RAM. The reconfiguration mechanism is done by a monitor tile placed along each cache banks. Experimental results on PARSEC benchmarks show that the propos...Show More
One of the main abilities that the robots need to maintain is to efficiently communicate with people in a humanly manner. Thus, human activity recognition (HAR) would be an integral part of such a human-robot interaction system. One of the major challenges in HAR is that the individuals perform their activities in different manners. Furthermore, there is a very wide range of different types of act...Show More
In this article, we present a convex optimization model to design a stacked hybrid memory system contains eDRAM and STT-RAM banks with minimum write energy consumption of STT-RAM memory banks and minimum refresh energy of eDRAM banks with efficient number of TSVs in embedded CMP. Our convex model optimizes numbers and placement of memory banks from different technologies on the memory layer and fi...Show More
In Nano-scale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM based on-chip cache memories. To address this issue, non-volatile memory technologies such as STT-RAM (Spin Transfer Torque-RAM) have been proposed as a replacement for SRAM cells due to their near zero static power consumption and high memory density. Nonetheless, STT-RAMs ...Show More
As the number of cores increases, power consumption becomes the main concern in Network on Chip (NoC) and Last Level Cache (LLC). In on-chip interconnection networks, bursty-based traffics between components such as cache and memory banks have a big contribution of total traffic in NoC-based many-core systems. In this context, these types of traffics have an impressive impact on NoC energy consump...Show More
In chip-multiprocessors with increasing the number of cores, power consumption becomes the main concern in Last Level Cache (LLC). Emerging technologies, such as three-dimensional integrated circuits (3D ICs) and non-volatile memories (NVMs) are among the newest solutions to the design of dark-silicon-aware multi/many-core systems. Although NVMs have many advantages like low leakage and high densi...Show More
In this paper, we propose a novel compression method called Zero-Duplicate Compression (ZDC) to compress network traffic and to increase lifetime in Non-Volatile Memories (NVMs) as a Last-Level-Cache (LLC). Moreover, we limit compression by a new mechanism called Selective Compression Architecture (SCA) to reduce delay overhead and static energy from compression/decompression. Our experiments show...Show More
This paper proposes a fast and reliable method for anomaly detection and localization in video data showing crowded scenes. Time-efficient anomaly localization is an ongoing challenge and subject of this paper. We propose a cubic-patch-based method, characterised by a cascade of classifiers, which makes use of an advanced feature-learning approach. Our cascade of classifiers has two main stages. F...Show More
Discriminating probabilistic graphical models are reliable tools for a sequence labeling task. Conditional Random Fields (CRFs) are discriminative models which will enable us to label a sequence of input data. Other variations of CRFs have been proposed. Hidden Conditional Random Fields (HCRFs) incorporate hidden states to the CRF model and assign a label for the whole input sequence as the model'...Show More
In this paper we introduce a general probabilistic graphical model for human everyday activity recognition. The proposed model is a discriminative graphical model with hidden variables for modeling body pose and sequential order of them. We use a unified framework for prediction task that is faster and more efficient than structured support vector machine and hidden conditional random fields. We h...Show More
By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become e...Show More
Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility....Show More
In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-transfer torque magnetic random-access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consu...Show More