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Lg = 60 nm In0.53 Ga0.47 As MBCFETs: From gm_max = 13.7 mS/üm and Q = 180 to virtual-source modeling
J.-H. Yoo;H.-B. Jo;I.-G. Lee;S.-M. Choi;J.-M. Baek;S T. Lee;H. Jang;M W. Kong;H H. Kim;H J. Lee;H.-J. Kim;H.-S. Jeong;W.-S. Park;D H. Ko;S. H. Shin;H.-M. Kwon;S K. Kim;J G. Kim;J. Yun;T. Kim;K.-Y. Shin;T.-W. Kim;J.-K. Shin;J.-H. Lee;C.-S. Shin;K.-S. Seo;D.-H. Kim
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
In this paper, we report scalable 5 -level stacked gate-all-around (GAA) In 0.53 Ga0.47As multi-bridge channel FETs (MBCFETs), with careful attention paid to fluorine migration. At its heart, we maintained temperature of all the unit process steps below 300 °C and inserted an n-InP ledge into a top ${In}_{0.52}\mathrm{Al}_{0.48}\mathrm{As}$ sacrificial layer to suppress $\mathrm{F}^{-}$-induced do...Show More
Lg = 60 nm In0.53 Ga0.47 As MBCFETs: From gm_max = 13.7 mS/üm and Q = 180 to virtual-source modeling
J.-H. Yoo;H.-B. Jo;I.-G. Lee;S.-M. Choi;J.-M. Baek;S T. Lee;H. Jang;M W. Kong;H H. Kim;H J. Lee;H.-J. Kim;H.-S. Jeong;W.-S. Park;D H. Ko;S. H. Shin;H.-M. Kwon;S K. Kim;J G. Kim;J. Yun;T. Kim;K.-Y. Shin;T.-W. Kim;J.-K. Shin;J.-H. Lee;C.-S. Shin;K.-S. Seo;D.-H. Kim
Year: 2023 | Conference Paper |
High-performance III–V devices for future logic applications
D.-H. Kim;T.-W. Kim;RH. Baek;P. D. Kirsch;W. Maszara;J. A. del Alamo;D. A. Antoniadis;M. Urteaga;B. Brar;HM. Kwon;C.-S. Shin;W.-K. Park;Y.-D. Cho;SH. Shin;DH. Ko;K.-S. Seo
2014 IEEE International Electron Devices Meeting
Year: 2014 | Conference Paper |
Cited by: Papers (19)
High-mobility III-V transistors are poised to take the lead on future high performance logic operation. If this happens, indium-rich InxGa1-xAs is the most promising n-channel material. Indeed, remarkable progress has been made, including III-V gate-stacks with ALD-grown gate dielectrics. This paper reviews the evolution of high-performance III-V devices for future logic applications and discuss a...Show More
Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s
C.-S. Shin;W.-K. Park;SH. Shin;YD. Cho;DH. Ko;T.-W. Kim;D.H. Koh;HM. Kwon;R. J. W. Hill;P. Kirsch;W. Maszara;D.-H. Kim
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
Year: 2014 | Conference Paper |
Cited by: Papers (3)
This paper reports on gate-last (GL) In0.7Ga0.3As QW MOSFETs with regrown S/D by MOCVD. Long-channel devices exhibit excellent electrostatics and carrier transport (SS=80mV/dec., DIBL=22mV/V, and μn,eff>5,500 cm2/V-s at 300k). Short-channel device with Lg = 40 nm also exhibit excellent electrostatic integrity of SS = 105 mV/dec., and DIBL = 150 mV/V, together with gm_max = 2 mS/μm at VDS = 0.5 V. ...Show More
Electrostatics and performance benchmarking using all types of III–V multi-gate FinFETs for sub 7nm technology node logic application
R.-H. Baek;D.-H. Kim;T.-W. Kim;CS. Shin;WK. Park;T. Michalak;C. Borst;S. C. Song;Geoffrey Yeap;R. Hill;C. Hobbs;W. Maszara;P. Kirsch
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
Year: 2014 | Conference Paper |
In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and ...Show More
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