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Silvio Simani - IEEE Xplore Author Profile

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Author details

Silvio Simani

Also published under: S. Simani

Publications

76

Citations

486

Publications by Year

19982025

Co-Authors:

Stefano AlvisiMatthew ArmstrongAma Baduba Asiedu-AsanteEdy AyalaP. Baldi

Show All Co-Authors (64)

Silvio Simani

Also published under: S. Simani

Affiliation

Department of Engineering

University of Ferrara

Ferrara, Italy

Publication Topics

Tracking Error,
Actuator Faults,
Control Input,
Fault Diagnosis,
Fault-tolerant Control,
Maximum Mean Discrepancy,
Neural Network,
Optimal Control,
Ablation Experiments,
Adaptive Control,
Basis Function Vector,
Control Objective

Biography

Silvio Simani (Senior Member, IEEE) received the M.Sc. degree in electronic engineering from the University of Ferrara, Ferrara, Italy, in 1996, and the Ph.D. degree in information sciences (automatic control area) from the University of Modena and Reggio Emilia, Modena, Italy, in 2000.,In 2002, he was an Assistant Professor with the Department of Engineering, University of Ferrara, where he has been an Associate Professor since 2014. His research interests include fault diagnosis, fault-tolerant control, and system identification, on which he has published about 160 refereed journal articles and conference papers, as well as three books and chapters.,Dr. Simani has been a member of the SAFEPROCESS Technical Committee since 2000.(Based on document published on 22 December 2023).

Publications

76

Citations

486

Publications by Year

19982025

Co-Authors:

Stefano Alvisi
Matthew Armstrong
Ama Baduba Asiedu-Asante
Edy Ayala
P. Baldi

Show All Co-Authors (64)

Author's Published Works

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Showing 1-5 of 5 results

Conferences (4)

Journals (1)

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Matthieu Dubois(5)
Salvador Mir(4)
Haralampos-G. Stratigopoulos(3)
Manuel J. Barragan(2)
Hervé Le Gall(1)
Pyxalis, Moirans, France(1)
CEA-LETI, Grenoble, France(1)
Sorbonne Universités, UPMC Univ. Paris 06, CNRS, LIP6, Paris, France(1)
TIMA Laboratory, CNRS-Grenoble INP, UJF, Grenoble, France(1)
Presto Engineering, Grenoble, France(1)
2009 IEEE International Conference on Computer Design(1)
2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop(1)
2012 IEEE International Test Conference(1)
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)(1)
IEEE Transactions on Circuits and Systems I: Regular Papers(1)
IEEE(5)
Anaheim, CA, USA(1)
Lake Tahoe, CA, USA(1)
Playa del Carmen, Mexico(1)
Taipei, Taiwan(1)
Analog-to-digital Converter(5)
Test Stimuli(4)
Behavioral Model(3)
Built-in Self-test(3)
Discrete Fourier Transform(3)

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A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Manuel J. Barragan;Rshdee Alhakim;Haralampos-G. Stratigopoulos;Matthieu Dubois;Salvador Mir;Hervé Le Gall;Neha Bhargava;Ankur Bal

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2016 | Volume: 63, Issue: 11 | Journal Article |

Cited by: Papers (18)

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This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a t...Show More

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Manuel J. Barragan;Rshdee Alhakim;Haralampos-G. Stratigopoulos;Matthieu Dubois;Salvador Mir;Hervé Le Gall;Neha Bhargava;Ankur Bal

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2016 | Volume: 63, Issue: 11 | Journal Article |

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir;Manuel J. Barragan

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

Year: 2014 | Conference Paper |

Cited by: Papers (4)

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Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of...Show More

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir;Manuel J. Barragan

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

Year: 2014 | Conference Paper |

A frequency measurement BIST implementation targeting gigahertz application

Matthieu Dubois;Emeric De Foucauld;Christopher Mounet;Sérigne Dia;Cédric Mayor

2012 IEEE International Test Conference

Year: 2012 | Conference Paper |

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In this paper we present a Built-In Self-Test (BIST) technique to measure the natural resonance frequency of oscillators which are design to set a much higher than the working speed of most of the current Automated Test Equipment (ATE). Based on an asynchronous counter, the BIST answers by a digital output code proportional to the frequency of the oscillator under test. The efficiency of the sugge...Show More

A frequency measurement BIST implementation targeting gigahertz application

Matthieu Dubois;Emeric De Foucauld;Christopher Mounet;Sérigne Dia;Cédric Mayor

2012 IEEE International Test Conference

Year: 2012 | Conference Paper |

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Matthieu Dubois;Haralampos G. Stratigopoulos;Salvador Mir

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop

Year: 2012 | Conference Paper |

Cited by: Papers (8) | Patents (2)

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In this paper, a ternary stimulus is proposed for testing ΣΔ Analog-to-Digital Converters (ADCs). The ternary stimulus is composed of three logic levels {-1,0,1} and is obtained by adding a binary stream with a delayed version of itself. Only four switches are added to the input stage of the modulator of the ΣΔ ADC for facilitating the injection of the ternary stimulus. Compared to a binary stimul...Show More

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Matthieu Dubois;Haralampos G. Stratigopoulos;Salvador Mir

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop

Year: 2012 | Conference Paper |

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir

2009 IEEE International Conference on Computer Design

Year: 2009 | Conference Paper |

Cited by: Papers (4)

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In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed...Show More

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir

2009 IEEE International Conference on Computer Design

Year: 2009 | Conference Paper |

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