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Song-Chun Zhu - IEEE Xplore Author Profile
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Song-Chun Zhu

Also published under: S. C. Zhu, Song-chun Zhu, Songchun Zhu

Publications
161
Citations
5,993
Publications by Year
20052025
Co-Authors:
Show All Co-Authors (192)
Image of author Song-Chun Zhu

Song-Chun Zhu

Also published under: S. C. Zhu, Song-chun Zhu, Songchun Zhu

Affiliation

Department of AI Music and Music Information Technology
Central Conservatory of Music
Beijing, China
State Key Laboratory of General Artificial Intelligence
BIGAI
Beijing, China

Publication Topics

Biography

Song-Chun Zhu (Fellow, IEEE) received the PhD degree from the Harvard University, Cambridge, Massachusetts, in 1996, and is currently a professor with the Departments of Statistics and Computer Science, UCLA. He has published more than 300 papers in computer vision, statistical modeling and learning, cognition, Language, robotics, and AI. He received a number of honors, including the Marr Prize in 2003, the Aggarwal prize from the International Association of Pattern Recognition in 2008, the Holmholtz Test-of-Time Prize in 2013, twice Marr Prize honorary nominations in 1999 and 2007, a Sloan Fellowship, the US NSF Career Award, and ONR Young Investigator Award in 2001.(Based on document published on 7 May 2020).
Publications
161
Citations
5,993
Publications by Year
20052025
Co-Authors:
Show All Co-Authors (192)
Author's Published Works

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A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio \Sigma\Delta ADC

Manuel J. Barragan;Rshdee Alhakim;Haralampos-G. Stratigopoulos;Matthieu Dubois;Salvador Mir;Hervé Le Gall;Neha Bhargava;Ankur Bal

IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2016 | Volume: 63, Issue: 11 | Journal Article |
Cited by: Papers (18)
This paper proposes a fully-digital BIST architecture for the dynamic test of ΣΔ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the ΣΔ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a t...Show More

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Manuel J. Barragan;Rshdee Alhakim;Haralampos-G. Stratigopoulos;Matthieu Dubois;Salvador Mir;Hervé Le Gall;Neha Bhargava;Ankur Bal

Year: 2016 | Volume: 63, Issue: 11 | Journal Article |

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir;Manuel J. Barragan

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
Year: 2014 | Conference Paper |
Cited by: Papers (4)
Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of...Show More

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir;Manuel J. Barragan

Year: 2014 | Conference Paper |

A frequency measurement BIST implementation targeting gigahertz application

Matthieu Dubois;Emeric De Foucauld;Christopher Mounet;Sérigne Dia;Cédric Mayor

2012 IEEE International Test Conference
Year: 2012 | Conference Paper |
In this paper we present a Built-In Self-Test (BIST) technique to measure the natural resonance frequency of oscillators which are design to set a much higher than the working speed of most of the current Automated Test Equipment (ATE). Based on an asynchronous counter, the BIST answers by a digital output code proportional to the frequency of the oscillator under test. The efficiency of the sugge...Show More

A frequency measurement BIST implementation targeting gigahertz application

Matthieu Dubois;Emeric De Foucauld;Christopher Mounet;Sérigne Dia;Cédric Mayor

Year: 2012 | Conference Paper |

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Matthieu Dubois;Haralampos G. Stratigopoulos;Salvador Mir

2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop
Year: 2012 | Conference Paper |
Cited by: Papers (8) | Patents (2)
In this paper, a ternary stimulus is proposed for testing ΣΔ Analog-to-Digital Converters (ADCs). The ternary stimulus is composed of three logic levels {-1,0,1} and is obtained by adding a binary stream with a delayed version of itself. Only four switches are added to the input stage of the modulator of the ΣΔ ADC for facilitating the injection of the ternary stimulus. Compared to a binary stimul...Show More

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Matthieu Dubois;Haralampos G. Stratigopoulos;Salvador Mir

Year: 2012 | Conference Paper |

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir

2009 IEEE International Conference on Computer Design
Year: 2009 | Conference Paper |
Cited by: Papers (4)
In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed...Show More

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study

Matthieu Dubois;Haralampos-G. Stratigopoulos;Salvador Mir

Year: 2009 | Conference Paper |

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