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Author details

Carlo C. Carobbi

Also published under: Carlo Carobbi, Carlo F. M. Carobbi, C. F. M. Carobbi, C. Carobbi, C. F. Carobbi

Publications

88

Citations

540

Publications by Year

19952024

Co-Authors:

Igor AizenbergLuk R. ArnautGilberto BassoMarco BindiA. Bonci

Show All Co-Authors (45)

Carlo C. Carobbi

Also published under: Carlo Carobbi, Carlo F. M. Carobbi, C. F. M. Carobbi, C. Carobbi, C. F. Carobbi

Affiliation

Dept. of Information Engineering

University of Florence

Firenze, Italy

Publication Topics

Reverberation Chamber,
Electromagnetic Compatibility,
Horn Antenna,
Vector Network Analyzer,
Antenna Efficiency,
Frequency Range,
Probability Density Function,
Arbitrary Waveform Generator,
Common Mode,
Common-mode Current,
Common-mode Voltage,
Correlation Structure

Biography

Carlo F. M. Carobbi (SM’15) was born in Pistoia, Italy, in 1968. He received the M.S. (cum laude) degree in electronic engineering and the Ph.D. degree in telematics from the University of Florence, Florence, Italy, in 1994 and 2000, respectively.,Since 2001, he has been a Researcher in the Department of information Engineering (formerly Department of Electronics and Telecommunications), University of Florence, where he teaches the course in electronic measurements. His current research interests include radio-frequency measurements and calculation of measurement uncertainty. He is chairman of the subcommittee 77B (electromagnetic compatibility, high-frequency phenomena) of the Italian Electrotechnical Committee and contributes to the...

Publications

88

Citations

540

Publications by Year

19952024

Co-Authors:

Igor Aizenberg
Luk R. Arnaut
Gilberto Basso
Marco Bindi
A. Bonci

Show All Co-Authors (45)

Author's Published Works

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Showing 1-25 of 97 results

Conferences (74)

Journals (23)

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Gaurav Trivedi(97)
Satyabrata Dash(13)
Sukumar Nandi(11)
Meenali Janveja(10)
Ashok Ray(9)
Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati, India(18)
Department of Electrical Engineering, University of Pardubice, Pardubice, Czech Republic(11)
Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, Guwahati, Assam, India(8)
Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati, India(6)
Department of Electronics and Electrical Engineering, Indian Institute of Technology, Guwahati, Assam, India(5)
2022 32nd International Conference Radioelektronika (RADIOELEKTRONIKA)(6)
IEEE Transactions on Circuits and Systems II: Express Briefs(6)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(5)
2016 International Conference on Accessibility to Digital World (ICADW)(4)
2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)(4)
IEEE(97)
Media(1)
Pardubice, Czech Republic(9)
Kosice, Slovakia(8)
Guwahati, India(5)
Kolkata, India(5)
Bhopal, India(4)
Power Consumption(20)
Hardware Implementation(14)
Neural Network(14)
Deep Neural Network(11)
Artificial Neural Network(9)

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Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications

Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2025 | Volume: 72, Issue: 1 | Journal Article |

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The sigmoid and

$hyperbolic\ tangent~(tanh)$ functions are widely recognized as the most commonly employed nonlinear activation functions in artificial neural networks. These functions incorporate exponential terms to introduce nonlinearity, which imposes significant challenges when realized on hardware. This brief presents a novel approach for the hardware implementation of sigmoid and tanh fun...Show More

Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications

Akash Dev Roshan;Prithwijit Guha;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2025 | Volume: 72, Issue: 1 | Journal Article |

Design of VTFET-Based Biosensor Utilizing Ambipolar Current in Detection Mechanism

Parmita Roy;Abhigyan Hazarika;Gaurav Trivedi

2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

Year: 2024 | Conference Paper |

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This work presents a vertical TFET -based biomolecule biosensor that utilizes ambipolar current of the VTFE T as a parameter for sensitivity measurement. Unlike conventional TFET biosensors, which capture biomolecules at the source side, the proposed biosensor is designed to capture biomolecules at the drain side. Additionally, the biomolecule receptors are positioned on an open sensing surface to...Show More

Design of VTFET-Based Biosensor Utilizing Ambipolar Current in Detection Mechanism

Parmita Roy;Abhigyan Hazarika;Gaurav Trivedi

2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)

Year: 2024 | Conference Paper |

Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow

Dhruva S. Hegde;Mandar Dalai;Manish Prajapati;Sachin B. Patkar;Gaurav Trivedi

2024 28th International Symposium on VLSI Design and Test (VDAT)

Year: 2024 | Conference Paper |

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Post-quantum cryptographic (PQC) algorithms are being standardized to prepare for the quantum computing era. CRYSTALS-Kyber is the chosen PQC scheme for Public Key Encryption. Number Theoretic Transforms (NTT) and SHA-3 core are the key primitives used in CRYSTALS-Kyber. Hence, fast and efficient implementations of these primitives are important. Typically, rapid prototyping of hardware blocks is ...Show More

Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow

Dhruva S. Hegde;Mandar Dalai;Manish Prajapati;Sachin B. Patkar;Gaurav Trivedi

2024 28th International Symposium on VLSI Design and Test (VDAT)

Year: 2024 | Conference Paper |

IoT-Enabled RC4-Stream-Cipher Powered Edge Data Encryption for Smart Home

Praveen Tiwari;Maria Kiran Kocherla;Shyra Nandanapu;Pinakeswar Mahanta;Gaurav Trivedi

2024 International Conference on Electrical, Computer and Energy Technologies (ICECET

Year: 2024 | Conference Paper |

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The research outlined in this paper focuses on designing and implementing a secure data transmission system within a smart home environment, utilizing the RC4-streamcipher (RSC) algorithm. The emphasis lies on integrating robust encryption mechanisms into sensor data, allowing for secure data aggregation directly at the edge through an IoT-enabled hardware setup. Within this system, sensor data un...Show More

IoT-Enabled RC4-Stream-Cipher Powered Edge Data Encryption for Smart Home

Praveen Tiwari;Maria Kiran Kocherla;Shyra Nandanapu;Pinakeswar Mahanta;Gaurav Trivedi

2024 International Conference on Electrical, Computer and Energy Technologies (ICECET

Year: 2024 | Conference Paper |

A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices

Meenali Janveja;Rushik Parmar;Srichandan Dash;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2024 | Volume: 32, Issue: 9 | Journal Article |

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Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classif...Show More

A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices

Meenali Janveja;Rushik Parmar;Srichandan Dash;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2024 | Volume: 32, Issue: 9 | Journal Article |

Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing

Bipul Boro;Rushik Parmar;Ashvinikumar Dongre;Gaurav Trivedi

2024 25th International Symposium on Quality Electronic Design (ISQED)

Year: 2024 | Conference Paper |

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Architectures utilizing Resistive Random-Access Memory (RRAM) for In-Memory Computing (IMC) have exhibited considerable potential in enhancing the performance metrics of neural networks (NNs). However, IMC configurations that incorporate Vector-Matrix Multipliers (VMMs) necessitate the incorporation of peripheral circuits such as Digital-to-Analog Converters (DAC) and Analog-to-Digital Converters ...Show More

Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing

Bipul Boro;Rushik Parmar;Ashvinikumar Dongre;Gaurav Trivedi

2024 25th International Symposium on Quality Electronic Design (ISQED)

Year: 2024 | Conference Paper |

An SNN-Inspired Area- and Power-Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices

Rushik Parmar;Khushil Yadav;Gauraangi Anand;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2024 | Volume: 71, Issue: 6 | Journal Article |

Cited by: Papers (1)

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Myocardial infarction (MI) is a cardiac abnormality in which the coronary artery gets blocked, causing millions of fatalities every year. MI has a very high mortality and disability rate; therefore, with the detection of MI, it is also imperative to determine the location of the blockage to provide on−time treatment to avoid any fatality. In this brief, for the first time, a VLSI architecture is p...Show More

An SNN-Inspired Area- and Power-Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices

Rushik Parmar;Khushil Yadav;Gauraangi Anand;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2024 | Volume: 71, Issue: 6 | Journal Article |

Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing

Bipul Boro;Ashvinikumar Dongre;Rushik Parmar;Gaurav Trivedi

2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Year: 2023 | Conference Paper |

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In-Memory Computing (IMC) architectures employing non-volatile memories (NMVs), such as RRAM, have shown considerable promise in improving the performance of artificial neural networks (ANNs) in terms of power and energy consumption. The Vector-Matrix Multipliers (VMM) used in IMC architectures require many peripheral circuits, such as Digital-to-Analog Converters (DAC) and Analog-to-Digital Conve...Show More

Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing

Bipul Boro;Ashvinikumar Dongre;Rushik Parmar;Gaurav Trivedi

2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Year: 2023 | Conference Paper |

Load-Data Imputation and Economic Feasibility Analysis of an Academic Institution

Praveen Tiwari;Shaik Asma;Navadeep Ganesh U;Pinakeswar Mahanta;Gaurav Trivedi

2023 International Conference on Electrical, Computer and Energy Technologies (ICECET)

Year: 2023 | Conference Paper |

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This study focuses on utilizing linear regression for imputing missing data in the context of electrical load profile analysis. Specifically, the study aims to utilize complete time series electric load profile data from the Indian Institute of Technology Guwahati (IITG) campus in Assam, India. The collected data is subjected to a linear regression analysis to impute missing values. The imputed da...Show More

Load-Data Imputation and Economic Feasibility Analysis of an Academic Institution

Praveen Tiwari;Shaik Asma;Navadeep Ganesh U;Pinakeswar Mahanta;Gaurav Trivedi

2023 International Conference on Electrical, Computer and Energy Technologies (ICECET)

Year: 2023 | Conference Paper |

ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing

Ashvinikumar Dongre;Bipul Boro;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 12 | Journal Article |

Cited by: Papers (1)

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Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory computing (IMC), have shown great potential in accelerating neural networks (NNs). However, existing IMC architectures rely on the area and power-hungry analog-to-digital converters (ADCs) for sensing the current, diminishing all the benefits of RRAM. Also, enhancing memory density is essential for implementing comp...Show More

ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing

Ashvinikumar Dongre;Bipul Boro;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 12 | Journal Article |

An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application

Meenali Janveja;Ashwani Kumar Sharma;Abhyuday Bhardwaj;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 12 | Journal Article |

Cited by: Papers (1)

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Continuous monitoring of the electrical activity of heart signals using wearable Internet of Healthcare Things (IoHTs) devices plays a crucial role in decreasing mortality rates. However, this continuous monitoring using an electrocardiogram (ECG) or vectorcardiogram (VCG) generates huge clinical data. Moreover, these devices are constrained in terms of ON-chip storage, data transmission capacity,...Show More

An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application

Meenali Janveja;Ashwani Kumar Sharma;Abhyuday Bhardwaj;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 12 | Journal Article |

FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box

Sushree Sila P. Goswami;Gaurav Trivedi

IEEE Embedded Systems Letters

Year: 2023 | Volume: 15, Issue: 4 | Journal Article |

Cited by: Papers (1)

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Security plays a vital role in electronic communication, particularly in wireless networks like long term evolution (LTE), where safeguarding data and resources from malicious activities is crucial. Cryptographic algorithms are at the core of security mechanisms, ensuring the protection of sensitive information. While software implementations of these algorithms are relatively straightforward, the...Show More

FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box

Sushree Sila P. Goswami;Gaurav Trivedi

IEEE Embedded Systems Letters

Year: 2023 | Volume: 15, Issue: 4 | Journal Article |

A Novel Dynamic Memristor Window Function for High Frequency Applications

Y. R. Ananda;Subhashis Das;Gaurav Trivedi

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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The window function plays an essential role in preserving the nonlinearity of the linear ion drift model of a memristor when the applied voltage and frequency are varied. This paper mainly focuses on designing a novel window function using a dynamic parameter suitable for various frequencies. Due to enhanced nonlinearity, the dynamic parameter eliminates the need for large static parameter values ...Show More

A Novel Dynamic Memristor Window Function for High Frequency Applications

Y. R. Ananda;Subhashis Das;Gaurav Trivedi

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

Year: 2023 | Conference Paper |

Variation Tolerant RRAM Based Synaptic Architecture for On-Chip Training

Ashvinikumar Dongre;Gaurav Trivedi

IEEE Transactions on Nanotechnology

Year: 2023 | Volume: 22 | Journal Article |

Cited by: Papers (1)

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Neuromorphic computing has emerged as a better alternative for developing next-generation artificial intelligent systems. Resistive Random Access Memory (RRAM) have been widely explored to represent the synaptic weights in artificial neural networks. Despite significant advances in device technology, precise modulation of conductance required for maintaining high accuracy remains a challenge. Thes...Show More

Variation Tolerant RRAM Based Synaptic Architecture for On-Chip Training

Ashvinikumar Dongre;Gaurav Trivedi

IEEE Transactions on Nanotechnology

Year: 2023 | Volume: 22 | Journal Article |

Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit

Ashvinikumar Dongre;Gaurav Trivedi

2023 24th International Symposium on Quality Electronic Design (ISQED)

Year: 2023 | Conference Paper |

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Resistive Random Access Memory (RRAM) is extensively used for the implementation of synapses. Even though a fresh metal oxide RRAM sampled in the pristine state cannot exhibit resistive switching before electroforming, the integration of the electroforming circuit in RRAM based applications has not been discussed thoroughly. A major challenge in integrating forming circuits is the high voltage req...Show More

Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit

Ashvinikumar Dongre;Gaurav Trivedi

2023 24th International Symposium on Quality Electronic Design (ISQED)

Year: 2023 | Conference Paper |

Hybrid multi-objective constrained optimization based on feasibility segregation, non-dominated sorting and crowding distance

Apurba Bikash Kalita;Subhash Chandra Rajbongshi;Gaurav Trivedi

2023 10th International Conference on Signal Processing and Integrated Networks (SPIN)

Year: 2023 | Conference Paper |

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In this work a hybrid technique is proposed to enable multi-objective Flower pollination algorithm, multi-objective Firefly algorithm and Multi-Objective Bat algorithm to cope with constrained optimization problems. This technique is based on feasibility segregation, non-dominated sorting and crowding distance adapted from non-dominated sorting genetic algorithm-II. Resulting three hybrid algorith...Show More

Hybrid multi-objective constrained optimization based on feasibility segregation, non-dominated sorting and crowding distance

Apurba Bikash Kalita;Subhash Chandra Rajbongshi;Gaurav Trivedi

2023 10th International Conference on Signal Processing and Integrated Networks (SPIN)

Year: 2023 | Conference Paper |

Comparison of Hardware Implementations of Cryptographic Algorithms for IoT Applications

Sushree Sila P. Goswami;Gaurav Trivedi

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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This paper compares various algorithms for application in the Internet of things (IoT). This technology contains a vast network of systems, sensors, and products, taking advantage of its low computing power and miniaturization of electronic networks and interconnected networks to provide extended capabilities that were not possible with the previouslyused technology. Many IoT devices per the custo...Show More

Comparison of Hardware Implementations of Cryptographic Algorithms for IoT Applications

Sushree Sila P. Goswami;Gaurav Trivedi

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Ankita Tiwari;Prithwijit Guha;Gaurav Trivedi;Nitesh Gupta;Navneeth Jayaraj;Jan Pidanic

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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The development of Machine Learning and IoT technology requires fast processing. RISC-V is an open-source reduced instruction set-based instruction set architecture, and the processor based on this architecture can be modified accordingly. The base integer instruction extension supports the operating system environment and is also suitable for embedded systems. It is a 32-bit instruction extension...Show More

IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Ankita Tiwari;Prithwijit Guha;Gaurav Trivedi;Nitesh Gupta;Navneeth Jayaraj;Jan Pidanic

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

An Adaptive Window Function based Memristor Model

Y. R. Ananda;Arkadeep Hajra;Gaurav Trivedi

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

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In the proposed work, a new window function for the memristor model is developed, incorporating an intelligent adaptive system. For the first time, an adaptive constant parameter for the window function is proposed in this paper, which introduces higher nonlinearity at the boundaries as compared to classical window functions. This parameter depends on the input voltage and frequency to generate a ...Show More

An Adaptive Window Function based Memristor Model

Y. R. Ananda;Arkadeep Hajra;Gaurav Trivedi

2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA)

Year: 2023 | Conference Paper |

Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices

Rushik Parmar;Meenali Janveja;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 3 | Journal Article |

Cited by: Papers (15)

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Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed ...Show More

Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices

Rushik Parmar;Meenali Janveja;Jan Pidanic;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 3 | Journal Article |

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

Ananda Y. R.;Nehal Raj;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 3 | Journal Article |

Cited by: Papers (8)

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The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correc...Show More

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

Ananda Y. R.;Nehal Raj;Gaurav Trivedi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 3 | Journal Article |

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications

Meenali Janveja;Rushik Parmar;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

Cited by: Papers (1)

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Myocardial Infarction (MI) is a critical heart abnormality causing millions of fatalities worldwide every year. MI progress in three stages based on its severity causing several changes in an Electrocardiogram (ECG) signal. It is very critical to capture these variations, which requires continuous monitoring of the ECG signal of the patient. Therefore, it becomes imperative to develop a low power ...Show More

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications

Meenali Janveja;Rushik Parmar;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

A High Frequency MOS-Based Floating Charge-Controlled Memcapacitor Emulator

Ananda Y. R.;Gadipelli Sriharsha Satyanarayan;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

Cited by: Papers (4)

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In this brief, a MOS-based memcapacitor emulator operating at $1.2~MHz$ is proposed. The analytical model of the proposed emulator is verified numerically and experimentally. Numerical analysis of the proposed memcapacitor with respect to various parameters is performed using $Cadence~Virtuoso$ with $TSMC~180~nm$ PDKs followed by post-layout simulation, which also validates its correctness. ...Show More

A High Frequency MOS-Based Floating Charge-Controlled Memcapacitor Emulator

Ananda Y. R.;Gadipelli Sriharsha Satyanarayan;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit

Ashvinikumar Dongre;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

Cited by: Papers (5)

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In this brief, we propose a Resistive Random Access Memory (RRAM) based self-resetting Integrate and Fire ( $\text{I}\&\text{F}$ ) neuron. The proposed neuron circuit does not require any external bias voltage and the integration of control unit required to reset RRAM into neuron circuit optimizes its overall power consumption. The neuron circuit proposed in this brief consists of two RRAMs for in...Show More

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit

Ashvinikumar Dongre;Gaurav Trivedi

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2023 | Volume: 70, Issue: 3 | Journal Article |

Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications

Bikram Paul;Angana Nath;Srinivasan Krishnaswamy;Jan Pidanic;Zdenek Nemec;Gaurav Trivedi

IEEE Transactions on Computers

Year: 2023 | Volume: 72, Issue: 6 | Journal Article |

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Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over $GF(2^{m})$GF(2m) and is...Show More

Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications

Bikram Paul;Angana Nath;Srinivasan Krishnaswamy;Jan Pidanic;Zdenek Nemec;Gaurav Trivedi

IEEE Transactions on Computers

Year: 2023 | Volume: 72, Issue: 6 | Journal Article |

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