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Qiang Qu - IEEE Xplore Author Profile

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Author details

Qiang Qu

Publications

2

Citations

35

Publications by Year

20222023

Co-Authors:

Xuewen DongSheng GaoYulong ShenWensheng TianMu Wang

Show All Co-Authors (12)

Qiang Qu

Affiliation

Shenzhen Institute of Advanced Techbology, Chinese Academy of Sciences

Huawei Blockchain Lab

Huawei Cloud Tech Co.

Ltd, Shenzhen, China

Publication Topics

Smart Contracts,
Arrival Rate,
Average Delay,
Balance Constraints,
Bandwidth Consumption,
Base Station,
CPU Usage,
Channel Size,
Communication Overhead,
Computation Tasks,
Computational Resources,
Computing Units

Biography

Qiang Qu is a Professor with the University of Chinese Academy of Sciences, with Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences. He is currently the Director of Blockchain Laboratory of Huawei Cloud Tech Company Ltd. His research interests include blockchain and data intensive systems.(Based on document published on 31 October 2022).

Publications

2

Citations

35

Publications by Year

20222023

Co-Authors:

Xuewen Dong
Sheng Gao
Yulong Shen
Wensheng Tian
Mu Wang

Show All Co-Authors (12)

Author's Published Works

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Showing 1-25 of 40 results

Conferences (20)

Journals (17)

Early Access Articles (3)

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Wenfeng Zhao(40)
Yajun Ha(17)
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Jian Xu(8)
Department of Biomedical Engineering, University of Minnesota, Minneapolis, MN, USA(9)
School of Information Science and Technology, ShanghaiTech University, Shanghai, China(6)
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China(5)
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing, China(5)
School of Electrical and Information Engineering, Tianjin University, Tianjin, China(4)
IEEE Transactions on Circuits and Systems II: Express Briefs(5)
2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)(4)
IEEE Transactions on Biomedical Circuits and Systems(4)
IEEE Transactions on Circuits and Systems I: Regular Papers(3)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(3)
IEEE(40)
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Shanghai, China(5)
Austin, TX, USA(1)
Beijing, China(1)
Boston, MA, USA(1)
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AdderNet 2.0: Optimal AdderNet Accelerator Designs With Activation-Oriented Quantization and Fused Bias Removal-Based Memory Optimization

Yunxiang Zhang;Omar Al Kailani;Bin Zhou;Wenfeng Zhao

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2025 | Early Access Article |

Convolutional neural networks (CNNs) are computationally demanding due to expensive Multiply-ACcumulate (MAC) operations. Emerging neural network models, such as AdderNet, exploit efficient arithmetic alternatives like sum-of-absolute-difference (SAD) operations to replace the costly MAC operations, while still achieving competitive model accuracy as compared with the CNN counterparts. Nevertheles...Show More

AdderNet 2.0: Optimal AdderNet Accelerator Designs With Activation-Oriented Quantization and Fused Bias Removal-Based Memory Optimization

Yunxiang Zhang;Omar Al Kailani;Bin Zhou;Wenfeng Zhao

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2025 | Early Access Article |

SpikeNAS-Bench: Benchmarking NAS Algorithms for Spiking Neural Network Architecture

Genchen Sun;Zhengkun Liu;Lin Gan;Hang Su;Ting Li;Wenfeng Zhao;Biao Sun

IEEE Transactions on Artificial Intelligence

Year: 2025 | Early Access Article |

In recent years, Neural Architecture Search (NAS) has marked significant advancements, yet its efficacy is marred by the dependence on substantial computational resources. To mitigate this, the development of NAS benchmarks has emerged, offering datasets that enumerate all potential network architectures and their performances within a predefined search space. Nonetheless, these benchmarks predomi...Show More

SpikeNAS-Bench: Benchmarking NAS Algorithms for Spiking Neural Network Architecture

Genchen Sun;Zhengkun Liu;Lin Gan;Hang Su;Ting Li;Wenfeng Zhao;Biao Sun

IEEE Transactions on Artificial Intelligence

Year: 2025 | Early Access Article |

BCIM: Constant-Time and High-Throughput Block-Cipher-In-Memory With Massively-Parallel Bit-Serial Execution

Andrew Dervay;Wenfeng Zhao

IEEE Transactions on Emerging Topics in Computing

Year: 2025 | Early Access Article |

In-memory computing (IMC) emerges as one of the most promising computing technologies for data-intensive applications to ameliorate the “memory wall” bottleneck in von Neumann computer systems. Meanwhile, IMC also shows promising prospects towards high- throughput and energy-efficient processing of cryptographic workloads. This paper presents Block-Cipher-In-Memory (BCIM), a constant-time, high- t...Show More

BCIM: Constant-Time and High-Throughput Block-Cipher-In-Memory With Massively-Parallel Bit-Serial Execution

Andrew Dervay;Wenfeng Zhao

IEEE Transactions on Emerging Topics in Computing

Year: 2025 | Early Access Article |

Compression of Respiratory Sound Signals via TranscoderQVAE

Jinglei Zhai;Wenfeng Zhao;Biao Sun

2024 IEEE Biomedical Circuits and Systems Conference (BioCAS)

Year: 2024 | Conference Paper |

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Respiratory diseases are one of the most common causes of death worldwide. At present, digital stethoscopes are valuable tools for diagnosing respiratory diseases, but they face limitations in storage, computation, and transmission capabilities. Therefore, developing respiratory sound compression algorithms is crucial. In this work, we propose TranscoderQVAE (TQVAE). TQVAE adopts the idea of varia...Show More

Compression of Respiratory Sound Signals via TranscoderQVAE

Jinglei Zhai;Wenfeng Zhao;Biao Sun

2024 IEEE Biomedical Circuits and Systems Conference (BioCAS)

Year: 2024 | Conference Paper |

Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief

Jiafeng Xie;Wenfeng Zhao;Hanho Lee;Debapriya Basu Roy;Xinmiao Zhang

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2024 | Volume: 71, Issue: 3 | Journal Article |

Cited by: Papers (7)

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Due to the increasing threats from possible large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from various communities recently. In particular, along with the National Institute of Standards and Technology (NIST) PQC standardization process, more works have gradually switched to the PQC hardware implementations. Following this trend, this tutorial brief...Show More

Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief

Jiafeng Xie;Wenfeng Zhao;Hanho Lee;Debapriya Basu Roy;Xinmiao Zhang

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2024 | Volume: 71, Issue: 3 | Journal Article |

An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet

Jian Xu;Anh Tuan Nguyen;Wenfeng Zhao;Wei Chen;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2024 | Volume: 18, Issue: 1 | Journal Article |

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Concurrent recording of neural activities and functional magnetic resonance imaging (fMRI) data is useful for studying the neurovascular coupling relationship. This article presents a low-noise, frequency-shaping based neural recorder chip that is insensitive to radio frequency (RF) pulses and gradient echo artifacts under strong magnetic environment. To support simultaneous recording of local fie...Show More

An MRI Compatible Data Acquisition Device for Rat Brain Recording Inside 16.4T Magnet

Jian Xu;Anh Tuan Nguyen;Wenfeng Zhao;Wei Chen;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2024 | Volume: 18, Issue: 1 | Journal Article |

WDVR-RAM: A 0.25–1.2 V, 2.6–76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads

Hongtu Zhang;Yuhao Shu;Qi Deng;Hao Sun;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2023 | Volume: 70, Issue: 10 | Journal Article |

Cited by: Papers (3)

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In-memory computing (IMC) is an effective approach to accelerate the interference tasks of binary neural networks (BNN), which has been widely used in artificial intelligence of things (AIoT) applications. However, previous researches only focus on optimizing energy efficiency for a narrow voltage range. This poses a severe limitation for some AIoT applications, because they may have very dynamic ...Show More

WDVR-RAM: A 0.25–1.2 V, 2.6–76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads

Hongtu Zhang;Yuhao Shu;Qi Deng;Hao Sun;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2023 | Volume: 70, Issue: 10 | Journal Article |

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation

Yuqi Wang;Shen Zhang;Yifei Li;Jian Chen;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 5 | Journal Article |

Cited by: Papers (6)

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Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based CSRAM designs. Existing solutions aim to mitigate the disturbance issue via weakening the access transistor strength, clampi...Show More

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation

Yuqi Wang;Shen Zhang;Yifei Li;Jian Chen;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2023 | Volume: 31, Issue: 5 | Journal Article |

WSQ-AdderNet: Efficient Weight Standardization based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization

Yunxiang Zhang;Biao Sun;Weixiong Jiang;Yajun Ha;Miao Hu;Wenfeng Zhao

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

Cited by: Papers (5)

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Convolutional neural networks (CNNs) have been widely adopted for various machine intelligence tasks. Nevertheless, CNNs are still known to be computational demanding due to the convolutional kernels involving expensive Multiply-ACcumulate (MAC) operations. Recent proposals on hardware-optimal neural network architectures suggest that AdderNet with a lightweight ℓ1-norm based feature extraction ke...Show More

WSQ-AdderNet: Efficient Weight Standardization based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization

Yunxiang Zhang;Biao Sun;Weixiong Jiang;Yajun Ha;Miao Hu;Wenfeng Zhao

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design

Yunxiang Zhang;Jian Xu;Miao Hu;Wenfeng Zhao

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

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This paper presents a hardware-efficient Saturation-Aware Compressed Sensing (SA-CS) encoder design exploiting the saturation arithmetic based accumulator architecture. The SA-CS encoder can label saturated measurements when a low-bitwidth accumulator is employed, thereby enabling the adoption of the saturation rejection CS recovery algorithm for successful signal reconstruction. Both the optimal ...Show More

Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design

Yunxiang Zhang;Jian Xu;Miao Hu;Wenfeng Zhao

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

Year: 2022 | Conference Paper |

CIMulator: A Computing in Memory Emulator Framework

Andrew Dervay;Wenfeng Zhao

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2022 | Volume: 69, Issue: 10 | Journal Article |

Cited by: Papers (4)

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In this brief, we present CIMulator, an open-source, extensible modeling, simulation, and emulation framework for on-chip digital Computing-In-Memory (CIM) design and assessment. Featuring a synthesizable Register Transfer Level (RTL) model, CIMulator encapsulates the fundamental in-memory bitline logic and the near-memory compute functionalities altogether. In this way, CIMulator ensures cycle-ac...Show More

CIMulator: A Computing in Memory Emulator Framework

Andrew Dervay;Wenfeng Zhao

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2022 | Volume: 69, Issue: 10 | Journal Article |

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yuhao Shu;Weixiong Jiang;Yajun Ha

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2022 | Volume: 30, Issue: 6 | Journal Article |

Cited by: Papers (24)

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To efficiently implement searching and logic functions with the SRAM-based in-memory computing (IMC), we need to perform computations on bitlines (BLs) (called compute access) via multiple wordline (WL) activations. However, this may cause prominent read disturbance when the IMC is implemented with the standard 6 T SRAM. To address this reliability issue, existing solutions adopt either auxiliary ...Show More

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yuhao Shu;Weixiong Jiang;Yajun Ha

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2022 | Volume: 30, Issue: 6 | Journal Article |

Artificial Intelligence Enables Real-Time and Intuitive Control of Prostheses via Nerve Interface

Diu Khue Luu;Anh Tuan Nguyen;Ming Jiang;Markus W. Drealan;Jian Xu;Tong Wu;Wing-kin Tam;Wenfeng Zhao;Brian Z. H. Lim;Cynthia K. Overstreet;Qi Zhao;Jonathan Cheng;Edward W. Keefer;Zhi Yang

IEEE Transactions on Biomedical Engineering

Year: 2022 | Volume: 69, Issue: 10 | Journal Article |

Cited by: Papers (17)

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Objective: The next generation prosthetic hand that moves and feels like a real hand requires a robust neural interconnection between the human minds and machines. Methods: Here we present a neuroprosthetic system to demonstrate that principle by employing an artificial intelligence (AI) agent to translate the amputee’s movement intent through a peripheral nerve interface. The AI agent is designed...Show More

Artificial Intelligence Enables Real-Time and Intuitive Control of Prostheses via Nerve Interface

Diu Khue Luu;Anh Tuan Nguyen;Ming Jiang;Markus W. Drealan;Jian Xu;Tong Wu;Wing-kin Tam;Wenfeng Zhao;Brian Z. H. Lim;Cynthia K. Overstreet;Qi Zhao;Jonathan Cheng;Edward W. Keefer;Zhi Yang

IEEE Transactions on Biomedical Engineering

Year: 2022 | Volume: 69, Issue: 10 | Journal Article |

Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yajun Ha

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2021 | Volume: 68, Issue: 12 | Journal Article |

Cited by: Papers (14)

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A compute SRAM requires high speed for both compute access and normal read access. However, it presents a very distinct bitline discharging behavior in these two modes, thus brings a significant challenge to the design of its sensing amplifiers. State-of-the-art sensing amplifiers, namely the symmetric single-ended sensing amplifier (SS-SA) and the asymmetric differential sensing amplifier (AD-SA)...Show More

Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yajun Ha

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2021 | Volume: 68, Issue: 12 | Journal Article |

A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications

Hongtu Zhang;Yuhao Shu;Weixiong Jiang;Zihan Yin;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2021 | Volume: 68, Issue: 5 | Journal Article |

Cited by: Papers (21)

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Binarized convolutional neural network (BCNN) is a promising and efficient technique toward the landscape of Artificial Intelligence of Things (AIoT) applications. In-Memory Computing (IMC) has widely been studied to accelerate the inference task of BCNN to maximize both throughput and energy efficiency. However, existing IMC circuits and architectures are only optimized for a fixed kernel size an...Show More

A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications

Hongtu Zhang;Yuhao Shu;Weixiong Jiang;Zihan Yin;Wenfeng Zhao;Yajun Ha

IEEE Transactions on Circuits and Systems II: Express Briefs

Year: 2021 | Volume: 68, Issue: 5 | Journal Article |

Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yajun Ha

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2021 | Volume: 68, Issue: 4 | Journal Article |

Cited by: Papers (33)

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In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either de...Show More

Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM

Jian Chen;Wenfeng Zhao;Yuqi Wang;Yajun Ha

IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2021 | Volume: 68, Issue: 4 | Journal Article |

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

Jian Xu;Anh Tuan Nguyen;Tong Wu;Wenfeng Zhao;Diu Khue Luu;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2020 | Volume: 14, Issue: 3 | Journal Article |

Cited by: Papers (18)

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A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, l...Show More

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor

Jian Xu;Anh Tuan Nguyen;Tong Wu;Wenfeng Zhao;Diu Khue Luu;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2020 | Volume: 14, Issue: 3 | Journal Article |

AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design

Wenfeng Zhao;Biao Sun;Jian Chen;Yajun Ha

2019 32nd IEEE International System-on-Chip Conference (SOCC)

Year: 2019 | Conference Paper |

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In this paper, we present an approximate computing framework for hardware-efficient compressed sensing encoder design exploiting application-level error-resiliency, termed as AxC-CS (Approximate Computing for Compressed Sensing). We consider a 2-stage scalar quantization scheme during CS encoding process for physiological signals in sensor nodes and demonstrate numerically that bringing forward th...Show More

AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design

Wenfeng Zhao;Biao Sun;Jian Chen;Yajun Ha

2019 32nd IEEE International System-on-Chip Conference (SOCC)

Year: 2019 | Conference Paper |

Block-Sparse Modeling for Compressed Sensing of Neural Action Potentials and Local Field Potentials

Wenfeng Zhao;Tong Wu;Jian Xu;Qi Zhao;Zhi Yang

2019 53rd Asilomar Conference on Signals, Systems, and Computers

Year: 2019 | Conference Paper |

Cited by: Papers (1)

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This paper presents our attempt for the efficient sparse modeling and recovery for Compressed Sensing (CS) of extracellular neural action and local field potentials (APs & LFPs). Both type of neural signals can be modeled as block-sparse in DCT (Discrete-Cosine Transform) domain, where we exploit the spectral information to determine the block boundaries, including bandpass filter pole information...Show More

Block-Sparse Modeling for Compressed Sensing of Neural Action Potentials and Local Field Potentials

Wenfeng Zhao;Tong Wu;Jian Xu;Qi Zhao;Zhi Yang

2019 53rd Asilomar Conference on Signals, Systems, and Computers

Year: 2019 | Conference Paper |

Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing

Jian Chen;Wenfeng Zhao;Yajun Ha

2019 IEEE 13th International Conference on ASIC (ASICON)

Year: 2019 | Conference Paper |

Cited by: Papers (3)

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Distributed arithmetic (DA) is popularly adopted in many digital signal processing (DSP) applications, such as filtering, linear transformations and convolutions, with both area and energy benefits. DA utilizes Look-Up Tables (LUTs) that are implemented with SRAM to store all possible precomputed results. However, a direct implementation will lead to exponential LUT size increase with respect to t...Show More

Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing

Jian Chen;Wenfeng Zhao;Yajun Ha

2019 IEEE 13th International Conference on ASIC (ASICON)

Year: 2019 | Conference Paper |

A Lightweight Deep Compressive Model for Large-Scale Spike Compression

Tong Wu;Wenfeng Zhao;Edward Keefer;Zhi Yang

2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)

Year: 2018 | Conference Paper |

Cited by: Papers (5)

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In this paper, we developed a deep learning-based compression model to reduce the data rate of multichannel action potentials in neural recording experiments. The proposed compression model is built upon a deep compressive autoencoder (CAE) with discrete latent embeddings. The encoder network of CAE is equipped with residual transformations to extract representative features from spikes, which are...Show More

A Lightweight Deep Compressive Model for Large-Scale Spike Compression

Tong Wu;Wenfeng Zhao;Edward Keefer;Zhi Yang

2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)

Year: 2018 | Conference Paper |

A Low-Noise, Wireless, Frequency-Shaping Neural Recorder

Jian Xu;Anh Tuan Nguyen;Wenfeng Zhao;Hongsun Guo;Tong Wu;Harvey Wiggins;Edward W. Keefer;Hubert Lim;Zhi Yang

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Year: 2018 | Volume: 8, Issue: 2 | Journal Article |

Cited by: Papers (21)

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This paper presents a low-noise, wireless neural recorder that has a frequency dependent amplification to remove electrode offset and to attenuate motion artifacts. The recorder has 2.5 GQ and 50 MQ input impedance at 20 Hz and 1 kHz for recording local field potentials and extracellular spikes, respectively. To reduce the input-referred noise, we propose a low-noise frontend design with multiple ...Show More

A Low-Noise, Wireless, Frequency-Shaping Neural Recorder

Jian Xu;Anh Tuan Nguyen;Wenfeng Zhao;Hongsun Guo;Tong Wu;Harvey Wiggins;Edward W. Keefer;Hubert Lim;Zhi Yang

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Year: 2018 | Volume: 8, Issue: 2 | Journal Article |

On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices

Wenfeng Zhao;Biao Sun;Tong Wu;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2018 | Volume: 12, Issue: 1 | Journal Article |

Cited by: Papers (42)

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On-chip neural data compression is an enabling technique for wireless neural interfaces that suffer from insufficient bandwidth and power budgets to transmit the raw data. The data compression algorithm and its implementation should be power and area efficient and functionally reliable over different datasets. Compressed sensing is an emerging technique that has been applied to compress various ne...Show More

On-Chip Neural Data Compression Based On Compressed Sensing With Sparse Sensing Matrices

Wenfeng Zhao;Biao Sun;Tong Wu;Zhi Yang

IEEE Transactions on Biomedical Circuits and Systems

Year: 2018 | Volume: 12, Issue: 1 | Journal Article |

BVF: Enabling Significant On-Chip Power Savings via Bit-Value-Favor for Throughput Processors

Ang Li;Wenfeng Zhao;Shuaiwen Leon Song

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Year: 2017 | Conference Paper |

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Power reduction is one of the primary tasks for designing modern processors, especially for high-performance throughput processors such as GPU due to their high power budget. In this paper, we propose a novel circuit-architecture co-design scheme to harvest enormous power savings for GPU on-chip SRAM and interconnects. We propose a new 8T SRAM that exhibits asymmetric energy consumption for bit va...Show More

BVF: Enabling Significant On-Chip Power Savings via Bit-Value-Favor for Throughput Processors

Ang Li;Wenfeng Zhao;Shuaiwen Leon Song

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Year: 2017 | Conference Paper |

Analysis and design of energy-efficient data-dependent SRAM

Wenfeng Zhao;Ang Li;Yi Wang;Yajun Ha

2017 IEEE 12th International Conference on ASIC (ASICON)

Year: 2017 | Conference Paper |

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Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and we...Show More

Analysis and design of energy-efficient data-dependent SRAM

Wenfeng Zhao;Ang Li;Yi Wang;Yajun Ha

2017 IEEE 12th International Conference on ASIC (ASICON)

Year: 2017 | Conference Paper |

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