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DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization
2022 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2022 | Conference Paper |
Cited by: Papers (11)
Process-In-Memory (PIM) is a promising solution to alleviating the memory-wall bottleneck in memory-intensive applications like CNNs. Recent demonstrations of SRAM-based PIM designs, particularly those computing in the charge domain [1]–[5], have greatly improved the linearity of analog multiply-and-add computations (MAC) and quantization, and their robustness to process variations, making their i...Show More
Teachers Do More Than Teach: Compressing Image-to-Image Models
Qing Jin;Jian Ren;Oliver J. Woodford;Jiazhuo Wang;Geng Yuan;Yanzhi Wang;Sergey Tulyakov
2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)
Year: 2021 | Conference Paper |
Cited by: Papers (36)
Generative Adversarial Networks (GANs) have achieved huge success in generating high-fidelity images, however, they suffer from low efficiency due to tremendous computational cost and bulky memory usage. Recent efforts on compression GANs show noticeable progress in obtaining smaller generators by sacrificing image quality or involving a time-consuming searching process. In this work, we aim to ad...Show More
NPAS: A Compiler-aware Framework of Unified Network Pruning and Architecture Search for Beyond Real-Time Mobile Acceleration
Zhengang Li;Geng Yuan;Wei Niu;Pu Zhao;Yanyu Li;Yuxuan Cai;Xuan Shen;Zheng Zhan;Zhenglun Kong;Qing Jin;Zhiyu Chen;Sijia Liu;Kaiyuan Yang;Bin Ren;Yanzhi Wang;Xue Lin
2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)
Year: 2021 | Conference Paper |
Cited by: Papers (15)
With the increasing demand to efficiently deploy DNNs on mobile edge devices, it becomes much more important to reduce unnecessary computation and increase the execution speed. Prior methods towards this goal, including model compression and network architecture search (NAS), are largely performed independently, and do not fully consider compiler-level optimizations which is a must-do for mobile a...Show More
NPAS: A Compiler-aware Framework of Unified Network Pruning and Architecture Search for Beyond Real-Time Mobile Acceleration
Zhengang Li;Geng Yuan;Wei Niu;Pu Zhao;Yanyu Li;Yuxuan Cai;Xuan Shen;Zheng Zhan;Zhenglun Kong;Qing Jin;Zhiyu Chen;Sijia Liu;Kaiyuan Yang;Bin Ren;Yanzhi Wang;Xue Lin
Year: 2021 | Conference Paper |
MC2-RAM: An In-8T-SRAM Computing Macro Featuring Multi-Bit Charge-Domain Computing and ADC-Reduction Weight Encoding
2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Year: 2021 | Conference Paper |
Cited by: Papers (12)
In-memory computing (IMC) is a promising hardware architecture to circumvent the memory walls in data-intensive applications, like deep learning. Among various memory technologies, static random-access memory (SRAM) is promising thanks to its high computing accuracy, reliability, and scalability to advanced technology nodes. This paper presents a novel multi-bit capacitive convolution in-SRAM comp...Show More
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference
Zhiyu Chen;Zhanghao Yu;Qing Jin;Yan He;Jingyu Wang;Sheng Lin;Dai Li;Yanzhi Wang;Kaiyuan Yang
A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adop...Show More
AdaBits: Neural Network Quantization With Adaptive Bit-Widths
2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)
Year: 2020 | Conference Paper |
Cited by: Papers (81)
Deep neural networks with adaptive configurations have gained increasing attention due to the instant and flexible deployment of these models on platforms with different resource budgets. In this paper, we investigate a novel option to achieve this goal by enabling adaptive bit-widths of weights and activations in the model. We first examine the benefits and challenges of training quantized model ...Show More
A 0.84pJ/cycle Wheatstone Bridge Based CMOS RC Oscillator with Reconfigurable Frequencies
2019 IEEE Custom Integrated Circuits Conference (CICC)
Year: 2019 | Conference Paper |
Cited by: Papers (16)
A low-power CMOS RC relaxation oscillator supporting reconfigurable frequencies is presented for timekeeping in low-power Internet of Things (IoT) devices. The oscillator employs a Wheatstone Bridge (WB) scheme to relax the constraint between reference current and reference resistance existing in prior arts. In addition, adjusting the resistor ratios in WB supports reconfigurable frequencies and a...Show More
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