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Jie Deng

Publications
7
Citations
10
Publications by Year
20192022
Co-Authors:
Show All Co-Authors (21)
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Jie Deng

Affiliation

State Key Laboratory of Disaster
Prevention & Reduction for Power Grid Transmission and Distribution Equipment
Changsha, China

Publication Topics

Biography

Jie Deng was born in Hunan, China, in 1993. He received his master's degree from Changsh University of Science and Technology, China, in 2020. Currently, he is studying for a PhD at Changsha University of Science and Technology. His research interest is on-line prevention of high-voltage power fire.(Based on document published on 17 August 2021).
Publications
7
Citations
10
Publications by Year
20192022
Co-Authors:
Show All Co-Authors (21)
Author's Published Works

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A 32GHz, 12.8GSps Direct Sampler and Converter for Direct Microwave Sampling for terrestrial and space applications

F. Boré;J. Duvernay;A. Landri;O. Legendre;J. Palmigiani;K. Salmi;A. Dezzani;S. Renane

2023 18th European Microwave Integrated Circuits Conference (EuMIC)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
Next generation communication standardization is calling for more flexibility with an access to higher carrier frequencies and wider instantaneous bandwidth. We propose to tackle these challenges by introducing wideband data converter solutions capable to directly access the microwave spectrum up to Q-band (40 \mathrm{GHz}). After a proof of concept presented at EuMW 2021, a product has been dev...Show More

A 32GHz, 12.8GSps Direct Sampler and Converter for Direct Microwave Sampling for terrestrial and space applications

F. Boré;J. Duvernay;A. Landri;O. Legendre;J. Palmigiani;K. Salmi;A. Dezzani;S. Renane

Year: 2023 | Conference Paper |

A NEMS-Array Control IC for Subattogram Mass Sensing Applications in 28 nm CMOS Technology

Nicolas Delorme;Christophe Le Blanc;Alessandro Dezzani;Mickaël Bély;Alexandre Ferret;Simon Laminette;Jérôme Roudier;Eric Colinet

IEEE Journal of Solid-State Circuits
Year: 2016 | Volume: 51, Issue: 1 | Journal Article |
Cited by: Papers (7)
The miniaturization and cost reduction of a gas chromatograph is addressed in this paper, leveraging on nanoelectromechanical systems (NEMS) detectors and a mixed-signal integrated circuit. The instrument and chip architectures are thoroughly described, characterized, and compared to other approaches like thermal conductivity detectors (TCDs). The 28 nm CMOS circuit addresses the sequential and pa...Show More

A NEMS-Array Control IC for Subattogram Mass Sensing Applications in 28 nm CMOS Technology

Nicolas Delorme;Christophe Le Blanc;Alessandro Dezzani;Mickaël Bély;Alexandre Ferret;Simon Laminette;Jérôme Roudier;Eric Colinet

Year: 2016 | Volume: 51, Issue: 1 | Journal Article |

16.5 A NEMS-array control IC for sub-attogram gravimetric sensing applications in 28nm CMOS technology

Nicolas Delorme;Christophe Le Blanc;Alessandro Dezzani;Mickaël Bely;Alexandre Ferret;Simon Laminette;Jérôme Roudier;Eric Colinet

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
Year: 2015 | Conference Paper |
Cited by: Papers (3)
Progress in silicon technology has promoted NEMS sensors as viable and highly sensitive candidates for gravimetric applications such as gas sensing, mass spectrometry and biochemical analysis [1]. The high sensitivity to mass is related to the small dimensions and intrinsic mass of the NEMS themselves, which results in resonant frequencies in the 10MHz-to-1GHz range and drive voltages reaching 1V ...Show More

16.5 A NEMS-array control IC for sub-attogram gravimetric sensing applications in 28nm CMOS technology

Nicolas Delorme;Christophe Le Blanc;Alessandro Dezzani;Mickaël Bely;Alexandre Ferret;Simon Laminette;Jérôme Roudier;Eric Colinet

Year: 2015 | Conference Paper |

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

Loic Joet;Alessandro Dezzani;Franck Montaudon;Franck Badets;Florent Sibille;Christian Corre;Laurent Chabert;Rayan Mina;Frederic Bailleuil;Daniel Saias;Frederic Paillardet;Ernesto Perea

2006 IEEE Asian Solid-State Circuits Conference
Year: 2006 | Conference Paper |
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-...Show More

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

Loic Joet;Alessandro Dezzani;Franck Montaudon;Franck Badets;Florent Sibille;Christian Corre;Laurent Chabert;Rayan Mina;Frederic Bailleuil;Daniel Saias;Frederic Paillardet;Ernesto Perea

Year: 2006 | Conference Paper |

A 120nm low power asynchronous ADC

E. Allier;J. Goulier;G. Sicard;A. Dezzani;E. Andre;M. Renaudin

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.
Year: 2005 | Conference Paper |
This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applicat...Show More

A 120nm low power asynchronous ADC

E. Allier;J. Goulier;G. Sicard;A. Dezzani;E. Andre;M. Renaudin

Year: 2005 | Conference Paper |

A 0.12 /spl mu/m CMOS DVB-T tuner

D. Saias;F. Montaudon;E. Andre;F. Bailleul;M. Bely;P. Busson;S. Dedieu;A. Dezzani;A. Moutard;G. Provins;E. Rouat;J. Roux;G. Wagner;F. Paillardet

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (7)
A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.Show More

A 0.12 /spl mu/m CMOS DVB-T tuner

D. Saias;F. Montaudon;E. Andre;F. Bailleul;M. Bely;P. Busson;S. Dedieu;A. Dezzani;A. Moutard;G. Provins;E. Rouat;J. Roux;G. Wagner;F. Paillardet

Year: 2005 | Conference Paper |

An Integrated DVD_T Tuner

F. Montaudon;D. Saias;A. Moutard;M. Bely;G. Provins;A. Dezzani;J. Roux;S. Dedieu;G. Wagner;E. Rouat;F. Bailleuil;P. Busson;E. Andre;F. Paillardet

The 3rd International IEEE-NEWCAS Conference, 2005.
Year: 2005 | Conference Paper |
A fully CMOS integrated DVB_T RF analog tuner achieving a 6.5 dB noise figure is presented. The tuner is implemented in a 0.12 mum CMOS process and occupies a 16 mm2 area. The receiver is based on a double zero IF conversion and integrates within the receiver chain the frequency synthesizers and two 4 MHz bandwidth 14 bit analog digital converters. The VCO exhibits a -140 dBc phase noise at 1 MHz ...Show More

An Integrated DVD_T Tuner

F. Montaudon;D. Saias;A. Moutard;M. Bely;G. Provins;A. Dezzani;J. Roux;S. Dedieu;G. Wagner;E. Rouat;F. Bailleuil;P. Busson;E. Andre;F. Paillardet

Year: 2005 | Conference Paper |

MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances

R. Difrenza;K. Rochereau;T. Devoivre;B. Tavel;B. Duriez;D. Roy;S. Jullian;A. Dezzani;R. Boulestin;P. Stolk;F. Arnaud

Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (5)
The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. A/sub Vt/ of 2.1 and 1.9 mV./spl mu/m for NMOS and PMOS respectively. We demonstrate that such results provide relevant circuit performance improvement. For SRAM, a gain of more than 50% has been achieved on cell r...Show More

MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances

R. Difrenza;K. Rochereau;T. Devoivre;B. Tavel;B. Duriez;D. Roy;S. Jullian;A. Dezzani;R. Boulestin;P. Stolk;F. Arnaud

Year: 2005 | Conference Paper |

A 1.2-V dual-mode WCDMA/GPRS /spl Sigma//spl Delta/ modulator

A. Dezzani;E. Andre

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
Year: 2003 | Conference Paper |
A dual-mode /spl Sigma//spl Delta/ modulator is designed to meet the specifications of a WCDMA/GPRS receiver and is composed of a single-bit second-order modulator followed by a multi-bit stage that adapts performance to broadband signals. The modulator achieves 82dB and 70dB of dynamic range over bandwidths of 100kHz and 1.92MHz, respectively, and dissipates 4.3mW from a 1.2V supply. The circuit ...Show More

A 1.2-V dual-mode WCDMA/GPRS /spl Sigma//spl Delta/ modulator

A. Dezzani;E. Andre

Year: 2003 | Conference Paper |

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