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VerC3: A library for explicit state synthesis of concurrent systems

Marco Elver;Christopher J. Banks;Paul Jackson;Vijay Nagarajan

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2018 | Conference Paper |

Cited by: Papers (6)

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We propose an alternative, explicit state only, approach to concurrent system synthesis. In particular, the focus of this work is on the synthesis of distributed protocols. Given a correctness specification and a protocol skeleton (i.e. incomplete with holes), the goal is to synthesize the holes. At the heart of our technique is a dynamic programming based algorithm that prunes inferred failure ca...Show More

VerC3: A library for explicit state synthesis of concurrent systems

Marco Elver;Christopher J. Banks;Paul Jackson;Vijay Nagarajan

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2018 | Conference Paper |

Verification of a lazy cache coherence protocol against a weak memory model

Christopher J. Banks;Marco Elver;Ruth Hoffmann;Susmit Sarkar;Paul Jackson;Vijay Nagarajan

2017 Formal Methods in Computer Aided Design (FMCAD)

Year: 2017 | Conference Paper |

Cited by: Papers (8)

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In this paper, we verify a modern lazy cache coherence protocol, TSO-CC, against the memory consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a novel finite-state operational model which exhibits the laziness of TSO-CC and satisfies TSO. We then extend this by an existing parameterisation t...Show More

Verification of a lazy cache coherence protocol against a weak memory model

Christopher J. Banks;Marco Elver;Ruth Hoffmann;Susmit Sarkar;Paul Jackson;Vijay Nagarajan

2017 Formal Methods in Computer Aided Design (FMCAD)

Year: 2017 | Conference Paper |

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