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Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement
Fatemehsadat Mahmoudi;Mohamed A. Elgammal;Soheil Gholami Shahrouz;Kevin E. Murray;Vaughn Betz
2023 International Conference on Field Programmable Technology (ICFPT)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
Simulated Annealing (SA) is widely used for FPGA placement due to its ability to adapt to different architectures and optimization goals. However, as FPGA capacity has grown and the devices have become more heterogeneous, the solution space has become very large, making efficient approaches to explore the space critical. We present RLPlace 2.0, an FPGA placer based on simulated annealing that util...Show More
VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization
Ruichen Chen;Shengyao Lu;Mohamed A. Elgammal;Peter Chun;Vaughn Betz;Di Niu
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
With the increasing complexity and capacity of modern Field-Programmable Gate Arrays (FPGAs), there is a growing demand for efficient FPGA computer-aided design (CAD) tools, particularly in the placement stage. While some previous works, such as RLPlace, have explored the efficacy of single-state Reinforcement Learning (RL) to optimize FPGA placement by framing it as a multi-armed bandit (MAB) pro...Show More
Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research
Aman Arora;Andrew Boutros;Seyed Alireza Damghani;Karan Mathur;Vedant Mohanty;Tanmay Anand;Mohamed A. Elgammal;Kenneth B. Kent;Vaughn Betz;Lizy K. John
the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing field-programmable gate array (FPGA) architecture and CAD to achieve better quality-of-results (QoRs) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and ...Show More
Quality & Generality: A Flexible FPGA Re-Clustering Technique to Improve Packing and Placement
2022 International Conference on Field-Programmable Technology (ICFPT)
Year: 2022 | Conference Paper |
The Packing and Placement stages are two major steps in the FPGA backend flow which greatly affect the Quality-of-Results (QoR) of design implementation. While these problems have been extensively studied in the literature, most approaches have either sacrificed generality by targeting specific and simplified FPGAs with few “block packing” legality constraints, or sacrificed quality by making irre...Show More
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement
Simulated annealing (SA) is one of the most common FPGA placement techniques, and is used both as a standalone algorithm and to improve an initial analytical placement. While SA-based placers can achieve high-quality results, they suffer from long runtimes. In this article, we introduce RLPlace, a novel SA-based FPGA placer that utilizes both reinforcement learning (RL) and targeted perturbations ...Show More
Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration
Heba Elhosary;Michael H. Zakhari;Mohamed A. Elgammal;Khaled A. Helal Kelany;Mohamed A. Abd El Ghany;Khaled N. Salama;Hassan Mostafa
In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of...Show More
SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs
Kevin E. Murray;Mohamed A. Elgammal;Vaughn Betz;Tim Ansell;Keith Rothman;Alessandro Comodi
As the benefits of Moore's Law diminish, computing performance, and efficiency gains are increasingly achieved through specializing hardware to a domain of computation. However, this limits the hardware's generality and flexibility. Field-programmable gate arrays (FPGAs), microchips which can be reprogrammed to implement arbitrary digital circuits, enable the benefits of specialization while remai...Show More
A Comparison of Artificial Neural Network(ANN) and Support Vector Machine(SVM) Classifiers for Neural Seizure Detection
Mohamed A. Elgammal;Hassan Mostafa;Khaled N. Salama;Ahmed Nader Mohieldin
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2019 | Conference Paper |
Cited by: Papers (13)
In this paper, two different classifiers are software and hardware implemented for neural seizure detection. The two techniques are support vector machine(SVM) and artificial neural networks(ANN). The two techniques are pretrained on software and only the classifiers are hardware implemented and tested. A comparison of the two techniques is performed on the levels of performance, energy consumptio...Show More
Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection
Heba Elhosary;Michael H. Zakhari;Mohamed A. Elgammal;Mohamed A. Abd El Ghany;Khaled N. Salama;Hassan Mostafa
In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and application speci...Show More
Optimal EEG Window Size for Neural Seizure Detection
2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)
Year: 2019 | Conference Paper |
Cited by: Papers (8)
In this paper, different window sizes for EEG signal segmentation are investigated in order to optimize the performance of seizure detection systems. To differentiate between epileptic and non-epileptic epochs, the time axis of the EEG signal is divided into non-overlapping windows. The window period should be long enough for the lapse to be informative but not too long for it to stay stationary. ...Show More
Linear and Nonlinear Feature Extraction for Neural Seizure Detection
Mohamed A. Elgammal;Omar A. Elkhouly;Heba Elhosary;Mohamed Elsayed;Ahmed Nader Mohieldin;Khaled N. Salama;Hassan Mostafa
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2018 | Conference Paper |
Cited by: Papers (11)
In this paper, both linear and nonlinear features have been reviewed with linear support vector machine (SVM) classifier for neural seizure detection. The work introduced in the paper includes performance measurement through different metrics: accuracy, sensitivity, and specificity of multiple linear and nonlinear features with linear support vector machine (SVM). A comparison is performed between...Show More
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