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Showing 1-25 of 39,811 resultsfor "Index Terms":Error check
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A new LDPC decoding algorithm aided by segmented cyclic redundancy checks for magnetic recording channels
We introduce a new low-density parity-check (LDPC) decoding algorithm that exploits the cyclic redundancy check (CRC) information of data segments. By using the error detection property of the CRC, we can successively decode data segments of a codeword corrupted by random errors and erasures. The key idea is that the messages from the variable nodes with correct checksum are fixed to deterministic...Show More
Error correction application of CRC in the RFID system
2011 International Conference on Business Management and Electronic Information
Year: 2011 | Conference Paper |
Cited by: Papers (4)
The application of CRC in the radio frequency identification protocol ISO15693 is analyzed. Based on CRC, the multiple bits error correction function is realized in the decode process of Manchester Code. The error correction principle and realization technique are described in detail. The selection of decision threshold and error correction bits is analyzed. The simulation and application results ...Show More
A multiple bits error correction method based on cyclic redundancy check codes
2008 9th International Conference on Signal Processing
Year: 2008 | Conference Paper |
Cited by: Papers (10)
A method which links the judge and data check is provided. The method realizes the ability of multiple bits error correction using cyclic redundancy check codes. The error correction principle and realization method are described in detail. The key parameters design of the method is analyzed. The simulation results show that the multiple bits error correction method can improve the bit error rate ...Show More
In this paper it is shown that Run-Length Limited Error Control Codes could be constructed from two and more-dimensional Single Parity Check Product Codes in case that at least one of the component codes has even codeword length. The main advantage is that this could be done without any additional redundancy and without modification of the encoding and decoding procedure used for the underlying er...Show More
Cyclic redundancy check code based high-rate error-detection code for perpendicular recording
We present a particular generator polynomial for a cyclic redundancy check (CRC) code that can be used to detect all dominant error events in perpendicular recording over a broad range of densities. This polynomial is also effective in detecting error events that occur at codeword boundaries. The bit-error-rate and the sector-error-rate performances are validated that result from the use of the co...Show More
Use of Low-Density Parity-Check Codes for Dominant Error Events Detection and k-Constraint Enforcement
In this paper, we propose to leverage the simple and explicit parity checks inherent in low-density parity-check (LDPC) codes to detect dominant error events without code rate penalty. This is enabled by enforcing a very weak constraint on the LDPC code parity check matrix structure. Such a constraint can be readily satisfied by most structured LDPC codes reported in the open literature, such as q...Show More
Improvement of Burst Error Correction Using a Look-Up Table with Low Density Parity Check Coding for Compressed Ultraspectral Sounder Data
2006 8th International Conference Advanced Communication Technology
Year: 2006 | Conference Paper |
Cited by: Patents (1)
Low density parity check (LDPC) codes have the ability to transmit data at rates approaching channel capacity with very low error probability. Our study of LDPC codes on JPEG2000-compressed ultraspectral sounder data shows that for an LDPC encoder designed with certain input parameters, the LDPC decoder is able to correct all single errors and two-bit burst errors. Furthermore, our analysis on a m...Show More
Adaptive FEC Codes Suitable for Variable Dimming Values in Visible Light Communication
IEEE Photonics Technology Letters
Cited by: Papers (45)
In this letter, we propose an adaptive forward error correction scheme based on low-density parity-check (LDPC) codes to efficiently adjust dimming values in visible light communication (VLC) systems. The proposed code is a quasi-cyclic LDPC code, in which extension and puncturing methods are used to maintain dimming control. The significant advantages of the proposed method are due to the lower n...Show More
Software Implementation of a Novel Approach to Improving Burst Errors Correction Capability of Hamming Code
2007 8th International Conference on Electronic Measurement and Instruments
Year: 2007 | Conference Paper |
Cited by: Papers (2)
Error correction coding has been a crucial part of data transmission or storage. In high-reliability applications, the single error correction and double error detections Hamming code may not provide adequate protection against burst errors. This makes multiple-error correction highly desirable. This paper proposed a novel approach to improving burst errors correction capability of the Hamming cod...Show More
An Unequal Error Protection Scheme of H.265 Video Stream in Unmanned Aerial Vehicle System
2021 7th International Conference on Computer and Communications (ICCC)
Year: 2021 | Conference Paper |
Under the technological development nowadays, bit error remains hard to be solved in Unmanned Aerial Vehicle (UAV) video transmission system. The common Equal Error Protection (EEP) scheme ignores the reality that the importance of different components of the video stream varies, leading to limitation of protection performance. This paper proposes an Unequal Error Protection (UEP) scheme of H.265 ...Show More
Bit Error Rate Performance Comparison of Low-Density Parity-Check Code and Polar Code
2023 29th International Conference on Telecommunications (ICT)
Year: 2023 | Conference Paper |
Cited by: Papers (2)
A fifth generation or 5G wireless communication is claimed to be able to upload data 20 times faster than 4G networks. With the introduction of 5G wireless communication, an error-correcting code is required to detect and reduce errors. From the many existing error-correcting codes, the Low-Density Parity Check (LDPC) Code and Polar Code were chosen because they have many advantages for 5G wireles...Show More
Robust-LDPC codes for Efficient Wireless Communication system: WiMAX Technology
2020 International Conference on Industry 4.0 Technology (I4Tech)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
In wireless Communication, there is a rapid growth of data transmission and it requires forward error correction approach in order to minimize the high bit-error-rates on transferred data in physical channel. In this study, our major aim is to reduce PAPR (Peak-to-Average Power Ratio) and BER (Bit Error Rate). The major difficulty is to proposed efficient forward error correction methods under noi...Show More
Advanced signal processing technique for storage systems
A post-Viterbi processor has found wide acceptance in recording systems since it can correct dominant error events at the channel detector output using only a few parity bits, and thereby significantly reduce the correction capacity loss of the error correction code. This paper presents two novel techniques for minimizing the mis-correction of a post-Viterbi processor based on an error detection c...Show More
Upper Bounds on the Rate of LDPC Codes for a Class of Finite-State Markov Channels
In this correspondence, we consider the class of finite-state Markov channels (FSMCs) in which the channel behaves as a binary symmetric channel (BSC) in each state. Upper bounds on the rate of LDPC codes for reliable communication over this class of FSMCs are found. A simple upper bound for all noninverting FSMCs is first derived. Subsequently, tighter bounds are derived for the special case of G...Show More
Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code
In prior researches, low-density-parity-check (LDPC) code is applied on high-speed magnetic random-access-memory (MRAM) for a better correctable bit error rate (CBER). However, on another emerging memory, resistive random-access-memory (RRAM), reset hard breakdown errors have high-reliability log-likelihood ratio (LLR) which significantly degrades LDPC code soft decision CBER and decoding iteratio...Show More
Burst error sensing scheme for page-oriented data
2016 International Conference on Information and Communication Technology Convergence (ICTC)
Year: 2016 | Conference Paper |
Burst error occurs due to various factors and degrades the system performance. In this paper, we propose a burst error sensing scheme for page-oriented data. Using this scheme, the proposed method can sense a two-dimensional burst error location. In addition, it is possible to improve the performance by using erasure decoding on the sensed burst error position.Show More
LDPC codes based on serially concatenated multiple parity-check codes
Marco Baldi;Giovanni Cancellieri;Andrea Carassai;Franco Chiaraluce
This letter proposes a new class of serially concatenated codes that can be viewed as low-density parity- check (LDPC) codes. They are derived from multiple serially concatenated single parity-check (M-SC-SPC) codes, but they use different components, that we call multiple parity-check (MPC) codes. In comparison with M-SC-SPC codes, the new scheme achieves better performance with similar complexit...Show More
Construction of Quantum LDPC Codes From Classical Row-Circulant QC-LDPCs
Zunaira Babar;Panagiotis Botsinis;Dimitrios Alanis;Soon Xin Ng;Lajos Hanzo
IEEE Communications Letters
Cited by: Papers (15)
Classical row-circulant quasi-cyclic (QC) low-density parity check (LDPC) matrices are known to generate efficient high-rate short and moderate-length QC-LDPC codes, while the comparable random structures exhibit numerous short cycles of length-4. Therefore, we conceive a general formalism for constructing nondual-containing Calderbank–Shor–Steane (CSS)-type quantum low-density parity check (QLDPC...Show More
Analog Iterative LDPC Decoder Based on Margin Propagation
A margin propagation (MP) algorithm that can be used for implementing analog decoders for low-density parity check (LDPC) codes is presented. Unlike conventional sum-product analog decoders that rely on translinear operation of transistors, MP decoders use addition, subtraction and threshold operations, and therefore can be mapped onto different analog circuit topologies (current-mode, charge-mode...Show More
Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect
T Siva Teja;T Sai Kiran;T.V.V Satya Narayana;M. Vinodhini;N. S. Murty
2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI)
Year: 2018 | Conference Paper |
Cited by: Papers (8)
In an On-chip communication where the devices have scaled down to nanometer scale, a single chip contains numerous processing elements and inter-communication between these elements is Network on chip. Glitches in NoC or the disturbances in the physical environment of NoC leads to multiple-bit errors. These leads to the loss of data communicated and may cause need for retransmission. Retransmitted...Show More
Binary Burst Error Correcting Cyclic Codes Designed with the Circulant Parity Check Matrix
IEEE Communications Letters
Cited by: Papers (3)
The letter presents binary cyclic codes with the maximum burst error correction capability. This is achieved based on the properties of circulant parity check matrix. Results conclude existence of codes with high minimum weight and rate greater than 0.28. It also gives cyclic product codes suitable for multiple burst and random error corrections.Show More
The single parity check (SPC) product code is one of the most popular error detection codes because it is easy to implement. But there are unrecoverable errors in the conventional two dimensional SPC product codes. To further improve the performance we propose cyclic redundancy check (CRC) assisted SPC product codes in this paper. The proposed CRC assisted SPC product codes can detect most of unre...Show More
On the error detection capability of combined LDPC and CRC codes for space telecommand transmissions
Marco Baldi;Nicola Maturo;Giacomo Ricciutelli;Franco Chiaraluce
2016 IEEE Symposium on Computers and Communication (ISCC)
Year: 2016 | Conference Paper |
Cited by: Papers (8)
We present a method for estimating the undetected error rate when a cyclic redundancy check (CRC) is performed on the output of the decoder of short low-density parity-check (LDPC) codes. This system is of interest for telecommand links, where new LDPC codes have been designed for updating the current standard. We show that these new LDPC codes combined with CRC are adequate for complying with the...Show More
Performance analysis of concatenated LDPC codes for video broadcast satellite system
2017 IEEE Radio and Antenna Days of the Indian Ocean (RADIO)
Year: 2017 | Conference Paper |
Cited by: Papers (5)
For the emerging digital video broadcast applications of satellite communication system, there is a demand to achieve the low bit error rate, reduced receiver end processing delay with high data rate transmission. Advance forward error correction techniques such as LDPC codes, Turbo codes and BCH codes can be employed to achieve this. LDPC code provides the high throughput, high data rate, improve...Show More
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