Vasileios Pezoulas - IEEE Xplore Author Profile

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A 9-bit current-mode SAR ADC for automatic power control of quad-channel vertical-cavity surface-emitting laser (VCSEL) optical transmitter is proposed in this paper. The ADC consists of an input selector, a current comparator, a 9-bit current-mode DAC, and clock generation and SAR logic control circuits. The good static characteristics of ADC are mainly implemented by using segmented DAC structur...Show More
This article presents a 2:1 analog multiplexer (AMUX) for a digital preprocessed analog-multiplexed digital-to-analog converter (DP-AM-DAC) in optical transmitter, which can generate a 160 GBaud (320 Gb/s) four-level pulse-amplitude modulation (PAM-4) signal. The AMUX was designed in 0.13μm BiCMOS technology that contains bipolar devices based on SiGe:C NPN-heterojunction bipolar transistor's (HBT...Show More
This paper presents a 4-level pulse amplitude modulation (PAM-4) linear driver for Mach-Zehnder Modulators (MZM) in 90-nm SiGe BiCMOS technology. The transmission line was employed in the input and output wiring to reduce the transmission loss of the high-speed signal. In addition, by adopting coupled inductor peaking technology and continuous time linear equalizer (CLTE), the bandwidth of system ...Show More
This paper presents a compact 56 Gb/s 4-level pulse amplitude modulation (PAM4) SerDes receiver, which employs a half rate architecture. By employing a LC voltage control oscillator (LC-VCO) based clock and data recovery (CDR), the jitter of the receiver is greatly reduced, and the complexity and noise of the system are also decreased. The CDR is implemented in a type-II bang-bang phase-locked loo...Show More
A 4:2 analog multiplexer (AMUX) for optical transmitters is presented, which can generate 80 GBaud(160 Gb/s) four-level pulse-amplitude modulation (PAM-4) signals with 2.4-V pp differential voltage swing at each output channel. The AMUX contains two 2:1 AMUX cells with fully differential configurations, and each AMUX cell consists of a clock input buffer, two data input buffers, an AMUX core, and ...Show More