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Lionel Nkenyereye - IEEE Xplore Author Profile

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Author details

Lionel Nkenyereye

Publications

13

Citations

159

Publications by Year

20172025

Co-Authors:

M. Abdullah-Al-WadudAtif AlamriKang-Jun BaegHika BarkiXiaoqing Chai

Show All Co-Authors (24)

Lionel Nkenyereye

Affiliation

Department of AI Convergence

Pukyong National University

Busan, Republic of Korea

Publication Topics

Deep Learning Models,
Accelerometer,
Computational Resources,
Continuous Monitoring,
Deep Learning,
Docker Container,
Edge Computing,
Edge Nodes,
Inertial Measurement Unit,
Multilayer Perceptron,
Performance Metrics,
Wearable Data

Biography

Lionel Nkenyereye received the B.S. degree in data communication from the High Institute of Technology, Burundi, in 2005, and the M.S. and Ph.D. degrees in computer engineering from Dong-Eui University, South Korea, in 2016 and 2019, respectively. Before joining Dong-Eui University, he was an Information Technology Officer with Finbank Burundi from 2012 to 2014. He was a Software Developer with Computer Applied Limited Burundi (CAL Burundi) from November 2008 to July 2012. His research interests include vehicular-to-everything communication, 5G and the IoT, software-defined networks, networked embedded systems, data communication, and vehicular networks.(Based on document published on 30 December 2019).

Publications

13

Citations

159

Publications by Year

20172025

Co-Authors:

M. Abdullah-Al-Wadud
Atif Alamri
Kang-Jun Baeg
Hika Barki
Xiaoqing Chai

Show All Co-Authors (24)

Author's Published Works

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Showing 1-5 of 5 results

Conferences (4)

Journals (1)

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V. Misra(5)
Bei Chen(5)
R. Jha(3)
S. Novak(2)
N. Biswas(2)
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, USA(4)
Department of Chemistry and Chemical Biology, State University of New Jersey, Rutgers, Piscataway, NJ, USA(1)
Intel assignee at SEMATECH, Austin, TX, USA(1)
Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC, USA(1)
Department of Electrical Engineering, North Carolina State University, Raleigh, NC, USA(1)
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.(2)
2005 International Semiconductor Device Research Symposium(1)
Digest. International Electron Devices Meeting,(1)
IEEE Electron Device Letters(1)
IEEE(5)
Washington, DC, USA(2)
Bethesda, MD, USA(1)
San Francisco, CA, USA(1)
Metal Gate(5)
Work Function(5)
Capping Layer(2)
Dielectric Interface(2)
Gate Electrode(2)

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Influence of oxygen diffusion through capping layers of low work function metal gate electrodes

Bei Chen;R. Jha;H. Lazar;N. Biswas;Jaehoon Lee;Bongmook Lee;L. Wielunski;E. Garfunkel;V. Misra

IEEE Electron Device Letters

Year: 2006 | Volume: 27, Issue: 4 | Journal Article |

Cited by: Papers (9)

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This letter evaluates Ru and W capping layers for MoTa metal gate electrodes in MOS capacitor applications. The authors report that the oxygen diffusion from the capping layer plays an important role in determining the MoTa alloy effective work function value on SiO/sub 2/. A MoTa alloy metal gate with Ru capping exhibits stable effective work function up to 900/spl deg/C annealing but is not stab...Show More

Influence of oxygen diffusion through capping layers of low work function metal gate electrodes

Bei Chen;R. Jha;H. Lazar;N. Biswas;Jaehoon Lee;Bongmook Lee;L. Wielunski;E. Garfunkel;V. Misra

IEEE Electron Device Letters

Year: 2006 | Volume: 27, Issue: 4 | Journal Article |

Ni/sub x/Ta/sub 1-x/Si and Ni/sub x/Pt/sub 1-x/Si ternary alloys for work function tuning on SiO/sub 2/, HfSiO/sub x/ and HfO/sub 2/ dielectrics

N. Biswas;S. Novak;Bei Chen;D. Lichtenwalner;M. Ozturk;V. Misra

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Year: 2005 | Conference Paper |

Cited by: Papers (1) | Patents (3)

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We present two new ternary alloy silicides with tunable work function ranging between 4.27eV to 4.7eV and 4.8eV to 5.0eV respectively for dual metal gate CMOS applications. NixTa1-xSi gates were investigated for NMOS and NixPt1-xSi gates were investigated for PMOS applications on SiO2, HfO 2 and HfSiOx dielectrics. A large degree of tuning was observed on SiO2 however the tuning range decreased as...Show More

Ni/sub x/Ta/sub 1-x/Si and Ni/sub x/Pt/sub 1-x/Si ternary alloys for work function tuning on SiO/sub 2/, HfSiO/sub x/ and HfO/sub 2/ dielectrics

N. Biswas;S. Novak;Bei Chen;D. Lichtenwalner;M. Ozturk;V. Misra

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Year: 2005 | Conference Paper |

Dependence of pmos metal work functions on surface conditions of high-k gate dielectrics

R. Jha;Bongmook Lee;Bei Chen;S. Novak;P. Majhi;V. Misra

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Year: 2005 | Conference Paper |

Cited by: Papers (8)

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The effective work function of PMOS metal gate electrode as a function of intentionally altered HfO2 surfaces was investigated. The impact of capping layers, diffusion barriers and interfacial layers on the final work function was also examined. The factors responsible for the change in the effective work function after subsequent thermal treatments were identified and routes to maintain the high ...Show More

Dependence of pmos metal work functions on surface conditions of high-k gate dielectrics

R. Jha;Bongmook Lee;Bei Chen;S. Novak;P. Majhi;V. Misra

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Year: 2005 | Conference Paper |

Work Function Tuning Via Ultra Thin Charged Reaction Layers Using AlTa and AlTaN Alloys

Bei Chen;R. Jha;V. Misra

2005 International Semiconductor Device Research Symposium

Year: 2005 | Conference Paper |

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First Page of the Article

Work Function Tuning Via Ultra Thin Charged Reaction Layers Using AlTa and AlTaN Alloys

Bei Chen;R. Jha;V. Misra

2005 International Semiconductor Device Research Symposium

Year: 2005 | Conference Paper |

Tunable work function dual metal gate technology for bulk and non-bulk CMOS

JaeHoon Lee;Huicai Zhong;You-Seok Suh;G. Heuss;J. Gurganus;Bei Chen;V. Misra

Digest. International Electron Devices Meeting,

Year: 2002 | Conference Paper |

Cited by: Papers (17) | Patents (5)

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This paper describes a metal gate process, which provides tunable work function values and ease of integration for dual metal gate process flow. Vertical stacks of Ru and Ta layers were subjected to high temperature anneals to promote intermixing which resulted in /spl phi//sub m/ tuning. It was found that Ru/Ta stacks provided up to 0.4 eV reduction in /spl phi//sub m/ compared to Ru. To increase...Show More

Tunable work function dual metal gate technology for bulk and non-bulk CMOS

JaeHoon Lee;Huicai Zhong;You-Seok Suh;G. Heuss;J. Gurganus;Bei Chen;V. Misra

Digest. International Electron Devices Meeting,

Year: 2002 | Conference Paper |

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