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Diego Cabrera

Also published under: Diego R. Cabrera, D. Cabrera

Publications
41
Citations
352
Publications by Year
20152025
Co-Authors:
Show All Co-Authors (71)
Image of author Diego Cabrera

Diego Cabrera

Also published under: Diego R. Cabrera, D. Cabrera

Affiliation

School of Mechanical Engineering
Dongguan University of Technology
Dongguan, China

Publication Topics

Biography

Diego Cabrera received the B.Sc. degree in electronic engineering from the Universidad Politécnica Salesiana, Ecuador, in 2012, and the M.Sc. degree in logic, computation, and artificial intelligence and the Ph.D. degree in computer science from Seville University, Spain, in 2014 and 2018, respectively. He is currently a Postdoctoral Fellow with the Dongguan University of Technology, China. He has been a Professor with the Universidad Politécnica Salesiana, since 2014. His research interests include intelligent systems, data-driven modeling, and fault diagnosis.(Based on document published on 20 May 2019).
Publications
41
Citations
352
Publications by Year
20152025
Co-Authors:
Show All Co-Authors (71)
Author's Published Works

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Reconfigurable wide-band receiver with positive feed-back translational loop

Christian Izquierdo;Andreas Kaiser;Franck Montaudon;Philippe Cathelin

2011 IEEE Radio Frequency Integrated Circuits Symposium
Year: 2011 | Conference Paper |
A wide-band receiver for multi-band multi-standard cellular applications with a positive feed-back translational loop is presented in this paper. This technique allows tunable RF filtering right on the input node of the LNA with the base-band filter selectivity. The architecture is highly reconfigurable both regarding the RF channel center frequency and the channel bandwidth. The 65nm CMOS prototy...Show More

Reconfigurable wide-band receiver with positive feed-back translational loop

Christian Izquierdo;Andreas Kaiser;Franck Montaudon;Philippe Cathelin

Year: 2011 | Conference Paper |

Wide-band receiver architecture with flexible blocker filtering techniques

Christian Izquierdo;Andreas Kaiser;Franck Montaudon;Philippe Cathelin

2010 17th IEEE International Conference on Electronics, Circuits and Systems
Year: 2010 | Conference Paper |
Cited by: Papers (1) | Patents (4)
Wide-band filterless RF front-ends are yet unpractical because of the stringent linearity requirements imposed by out-of-band blockers. A base-band to radio-frequency feedback receiver (BB-RF-FBRX) architecture is proposed in this paper, which reflects the base-band selectivity to the RF input. The aim of this architecture is to eliminate surface acoustic wave (SAW) filters between the antenna and...Show More

Wide-band receiver architecture with flexible blocker filtering techniques

Christian Izquierdo;Andreas Kaiser;Franck Montaudon;Philippe Cathelin

Year: 2010 | Conference Paper |

A 1.3V 26mW 3.2GS/s undersampled LC bandpass ΣΔ ADC for a SDR ISM-band receiver in 130nm CMOS

Nicolas Beilleau;Hassan Aboushady;Franck Montaudon;Andreia Cathelin

2009 IEEE Radio Frequency Integrated Circuits Symposium
Year: 2009 | Conference Paper |
This paper presents the implementation of an undersampled LC bandpass SigmaDelta ADC with a raised-cosine feedback DAC. It directly converts after the LNA a signal centered in the ISM band at 2.442 GHz with a sampling frequency of 3.256 GHz. This circuit has been fabricated in a 130 nm CMOS process, it occupies an area of 0.27 mm2 and is operating at a supply voltage of 1.3 V. The Signal-to-Noise ...Show More

A 1.3V 26mW 3.2GS/s undersampled LC bandpass ΣΔ ADC for a SDR ISM-band receiver in 130nm CMOS

Nicolas Beilleau;Hassan Aboushady;Franck Montaudon;Andreia Cathelin

Year: 2009 | Conference Paper |

A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Franck Montaudon;Rayan Mina;Stephane Le Tual;Loic Joet;Daniel Saias;Razak Hossain;Florent Sibille;Christian Corre;Valerie Carrat;Emmanuel Chataigner;Jerome Lajoinie;Sebastien Dedieu;Frederic Paillardet;Ernesto Perea

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
Year: 2008 | Conference Paper |
Cited by: Papers (13)
While CMOS technology has fueled continued progress in digital baseband scalability, analog functions still need considerable design effort. Therefore, a fully integrated scalable radio receiver should exploit simplified analog design, have no restriction to supply voltage scaling and enable co-integration of RF, analog and digital functions. Switching speed is the main MOS device performance that...Show More

A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Franck Montaudon;Rayan Mina;Stephane Le Tual;Loic Joet;Daniel Saias;Razak Hossain;Florent Sibille;Christian Corre;Valerie Carrat;Emmanuel Chataigner;Jerome Lajoinie;Sebastien Dedieu;Frederic Paillardet;Ernesto Perea

Year: 2008 | Conference Paper |

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

Loic Joet;Alessandro Dezzani;Franck Montaudon;Franck Badets;Florent Sibille;Christian Corre;Laurent Chabert;Rayan Mina;Frederic Bailleuil;Daniel Saias;Frederic Paillardet;Ernesto Perea

2006 IEEE Asian Solid-State Circuits Conference
Year: 2006 | Conference Paper |
A new discrete-time receiver architecture enables to specifically circumvent CMOS integration issues, taking advantage of ZIF architectures yet escaping impact of flicker noise and second-order front-end non-linearity. This architecture, compatible with further scaling, was implemented for a GSM receiver in 90-nm CMOS. This receiver occupies 1-mm2 core area, achieves -108-dBm sensitivity, and -16-...Show More

Advanced `Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS

Loic Joet;Alessandro Dezzani;Franck Montaudon;Franck Badets;Florent Sibille;Christian Corre;Laurent Chabert;Rayan Mina;Frederic Bailleuil;Daniel Saias;Frederic Paillardet;Ernesto Perea

Year: 2006 | Conference Paper |

A 0.12 /spl mu/m CMOS DVB-T tuner

D. Saias;F. Montaudon;E. Andre;F. Bailleul;M. Bely;P. Busson;S. Dedieu;A. Dezzani;A. Moutard;G. Provins;E. Rouat;J. Roux;G. Wagner;F. Paillardet

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
Year: 2005 | Conference Paper |
Cited by: Papers (7)
A DVB-T tuner is integrated in 0.12 /spl mu/m CMOS. The 16mm/sup 2/ chip integrates a double conversion chain including PLL, VCO, voltage regulators, and ADC. The receiver exhibits a 6.5dB NF, a VCO phase noise of -140dBc/Hz at 1MHz offset at 1.21GHz, and a 14b ADC. It is compatible for integration with a digital demodulator IP.Show More

A 0.12 /spl mu/m CMOS DVB-T tuner

D. Saias;F. Montaudon;E. Andre;F. Bailleul;M. Bely;P. Busson;S. Dedieu;A. Dezzani;A. Moutard;G. Provins;E. Rouat;J. Roux;G. Wagner;F. Paillardet

Year: 2005 | Conference Paper |

An Integrated DVD_T Tuner

F. Montaudon;D. Saias;A. Moutard;M. Bely;G. Provins;A. Dezzani;J. Roux;S. Dedieu;G. Wagner;E. Rouat;F. Bailleuil;P. Busson;E. Andre;F. Paillardet

The 3rd International IEEE-NEWCAS Conference, 2005.
Year: 2005 | Conference Paper |
A fully CMOS integrated DVB_T RF analog tuner achieving a 6.5 dB noise figure is presented. The tuner is implemented in a 0.12 mum CMOS process and occupies a 16 mm2 area. The receiver is based on a double zero IF conversion and integrates within the receiver chain the frequency synthesizers and two 4 MHz bandwidth 14 bit analog digital converters. The VCO exhibits a -140 dBc phase noise at 1 MHz ...Show More

An Integrated DVD_T Tuner

F. Montaudon;D. Saias;A. Moutard;M. Bely;G. Provins;A. Dezzani;J. Roux;S. Dedieu;G. Wagner;E. Rouat;F. Bailleuil;P. Busson;E. Andre;F. Paillardet

Year: 2005 | Conference Paper |

A 5mW, 100kHz bandwidth, current-mode continuous-time Σ -Δ modulator with 84 dB dynamic range

H. Aboushady;F. Montaudon;F. Paillardet;M.M. Louerat

Proceedings of the 28th European Solid-State Circuits Conference
Year: 2002 | Conference Paper |
This current-mode continuous-time ΣΔ modulator achieves 84dB dynamic range. With a sampling frequency of 26MHz, the modulator consumes 5mW at 1.8V. The peak SNR is 79dB in 100kHz bandwidth. The Total Harmonic Distortion is -79dB for 25kHz input signal. The fully differential third order modulator is implemented in 0.18µm CMOS process with polysilicon n-well capacitors, and occupies 1.56mm2.Show More

A 5mW, 100kHz bandwidth, current-mode continuous-time Σ -Δ modulator with 84 dB dynamic range

H. Aboushady;F. Montaudon;F. Paillardet;M.M. Louerat

Year: 2002 | Conference Paper |

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