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Yuxin Sun - IEEE Xplore Author Profile

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Modern high reliability EEPROM technologies use advanced screening methods to screen out weak bit cells. In combination with standard ECC (Error Correction Code) methods EEPROMs can be produced to withstand more than 50k endurance cycles at 150°C and have a data retention of 10 years at 150°C. Both the number of endurance cycles and the data retention define the lifetime of an EEPROM memory. After...Show More
This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and co...Show More
We describe a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters. An unsupervised biclustering technique is then utilized to extract grayscale and binary spatial patterns from...Show More
In order to manufacture high quality and cost effective EEPROMs suitable for automotive under-hood applications several topics must be taken into account. As well as a high reliability EEPROM technology the choice of an advanced memory architecture including ECC and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM product...Show More
In modern automotive designs double contacts are mandatory to achieve high reliability products and avoid field returns due to contact issues during the lifetime of the product. Using double contacts in compact digital IPs like RAM, ROM or NVMs leads to a dramatic area penalty. High area efficient NMVs are using shared contacts to minimize the area needed to realize the NVM bit cells. Using double...Show More
Within this work the complete design and characterization of a 10bit Analog to Digital Converter (ADC) for a sample rate up to 100MSps is presented. Therefore pipeline architecture with a series of 1.5bit stages has been realized. Each stage contains a sub-ADC (two high speed comparators and a latch) and a multiplying DAC (switched capacitor feedback circuit with a high gain folded cascode operati...Show More
This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical ...Show More
The existing embedded nonvolatile memory technologies have failed to deliver a cost effective solution for SoC applications. The major reason has been that most of these technologies were not designed specifically for the embedded applications. There have been two approaches for the embedded nonvolatile memories. One is to take the high density stand alone memory technology and use it for embedded...Show More
A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range...Show More