A Monolithic Differential Bridged T-Coil

Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and $7~{\pm }~2$ ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and $12~{\pm }~2$ -ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is $2.43\times $ (MFA) and $2.2\times $ (MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of $224 \times 215~{\mu {\text {m}}^{2}}$ .

I. Introduction

Inductive peaking coils facilitate the rapid charging and discharging of parasitic capacitances to extend the bandwidth () of amplifier circuits [1], [2], [3]. The greatest bandwidth extension ratio (BWER , where is unpeaked bandwidth) under 0-dB ripple and peaking conditions is realized with bridged T-coil peaking, which was originally developed for high-speed oscilloscopes [4]. On-chip, broadband terminations using T-coils [5] are often co-designed with ESD circuitry to protect high-speed I/Os [6], [7], [8], [9], [10]. Other applications include compact delay lines [11], [12], input impedance compensation [13], [14], and branch line couplers [15].