Chopper Instrumentation Amplifier Design With Fully Symmetric Loops for Input Impedance Boosting

This paper presents a chopper instrumentation amplifier (IA) architecture with two symmetric differential negative capacitance generation feedback (NCGFB) loops. The NCGFB design technique enables to cancel parasitic capacitances of cables and electrodes at the IA input in order to boost the input impedance. The negative capacitance is generated through feedback loops containing digitally programmable capacitor banks that can compensate for an extra input capacitance of up to 100 pF. A chopping technique is also introduced to enhance the noise performance of NCGFB IAs with input impedance boosting. The proposed amplifier is based on the capacitively-coupled IA (CCIA) architecture with additional circuit-level innovations to increase input impedance and improve noise performance. Two NCGFB loops have been added to further boost the input impedance. These NCGFB loops include a low-pass filter (LPF) to suppress ripples from the chopping prior to feeding the signal back to nodes at which capacitances are cancelled. We present an analysis to verify the stability of the loops as well as their effects on boosting the input impedance. The full symmetry of the NCGFB loops enables the use of identical capacitor banks to maintain a high common-mode rejection ratio (CMRR). The IA was designed and fabricated in 65-nm CMOS technology with a 1.2V supply and consumes
$2.46~\mu $
W. Chip measurements show that the IA has a 44-dB gain, 40-Hz bandwidth, a total harmonic distortion (THD) of −44.3 dB with 35 mVpp sinusoidal output at 10 Hz, CMRR >90.9 dB, a 92.3 dB power supply rejection ratio (PSRR), 0.54-
$\mu $
V integrated input-referred noise over a bandwidth of 0.5 - 40 Hz with a noise efficiency factor of 4.75, and an input impedance of 1.9 G
$\Omega $
at 10 Hz even with an extra input capacitance of 100 pF.