Area-Delay-Energy-Efficient Approximate Dividers Based on Piecewise Linear Fitting of Surface

In this paper, signed and unsigned approximate dividers based on piecewise linear fitting of surface (PLSAD) are proposed. After extracting the exponent and mantissa of two binary fixed-point operands, the surface representing the quotient of the mantissa is partitioned into sub-regions, which are linearly approximated by rectangular planes. The proposed logic architecture for geometric plane computations relies on simple arithmetic operations of addition and shifting. Additionally, approximate adders reduce circuit complexity and enhance performance, while enabling dynamic configuration of dividers based on accuracy requirements. Fairly compared to recently published approximated dividers based on the same 45nm technology and logic synthesis constrains, the proposed circuits outperform other works in overall aspects. ‘As the bit-width of OR-gate additions in Least significant bit (LSB) increases, the mean relative error distance (MRED) gradually grows from 0.82% to 2.63%, while the circuit area, delay and power consumption reduce to 840um2, 0.9ns and 881uW, respectively. Similarly, the proposed approximate floating-point (FP) 16-bit and 32-bit dividers improve circuit delay and power by over 50% compared to the state-of-the-art designs in the same condition. The proposed dividers perform well in image processing and demonstrate high adaptability in softmax layer of deep neural network and real-time EEG signal recognition applications.