Hardware-Efficient Multipliers With FPGA-Based Approximation for Error-Resilient Applications

Approximate multipliers enable hardware savings for error-resilient computation-intensive applications. Most existing approximate multipliers have been on ASIC-based circuits. They might not achieve comparable performance gains when used for FPGA-based accelerators. In this paper, we propose hardware-efficient FPGA-based accurate and approximate 4
$\bm{\times}$
4 multipliers with novel methodologies of look-up table (LUT) sharing and carry switching. The LUT resources can be fully utilized by sharing two LUTs with the same inputs. To compensate for the accuracy loss, the truncated carry is partially reserved by switching it to the adjacent calculation. For higher-order multipliers, three approximate adders are proposed to sum the result of the multipliers with arbitrary size. 140 types of 8
$\bm{\times}$
8 multipliers are constructed by combining the proposed 4
$\bm{\times}$
4 multipliers and adders, providing various multiplication choices for different demands. The proposed approximate 8
$\bm{\times}$
8 multiplier can achieve up to 38.75%, 17.29%, and 28.17% improvements in power, latency, and area over the Xilinx exact multiplier, respectively. Moreover, the proposed accurate and approximate 8
$\bm{\times}$
8 multipliers with different adders are extended to 16
$\bm{\times}$
16 multipliers. As evidenced by the performance of the 16
$\bm{\times}$
16 multipliers, our methodology demonstrates the capability to design higher-order multipliers flexibly. Compared with previous works under a similar accuracy loss, the proposed multiplier achieves more hardware savings. Furthermore, the approximate multipliers are assessed on the application of image processing to validate the practical applicability. We create a library of the proposed multipliers which is open-source at https://github.com/YnuGuoLab /Approx_Mul_FPGA/ and assist in further reproducing and development.