Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p+-Pocket Implant and Negative Capacitance for Enhanced Performance

In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p
⁺
-pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in I
_ON
/I
_OFF
and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p
⁺
-pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), I
_ON
/I
_OFF
ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.