PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout

Analog compute-in-memory (CIM) in static random access memory (SRAM) is promising for accelerating deep learning inference by circumventing the memory wall and exploiting ultra-efficient analog low-precision arithmetic. Latest analog CIM designs attempt bit-parallel (BP) schemes for multi-bit analog matrix-vector multiplication (MVM), aiming at higher energy efficiency, throughput, and training simplicity and robustness over conventional bit-serial (BS) methods that digitally shift-and-add multiple partial analog computing results. However, BP operations require more complex analog computations and become more sensitive to well-known analog CIM challenges, including large cell areas, inefficient and inaccurate multi-bit analog operations, and vulnerability to PVT variations. This article presents PICO-RAM, a PVT-insensitive and compact CIM SRAM macro with charge-domain BP computation. It adopts a multi-bit thin-cell multiply-accumulate (MAC) unit that shares the same transistor layout as the most compact 6T SRAM cell. All analog computing modules, including digital-to-analog converters (DACs), MAC units, analog shift-and-add, and analog-to-digital converters (ADCs), reuse one set of local capacitors inside the array, performing in situ computation to save area and enhance accuracy. A compact 8.5-bit dual-threshold time-domain ADC power gates the main path most of the time, leading to a significant energy reduction. Our 65-nm prototype achieves the highest weight storage density of 559 Kb/mm
$^2$
and exceptional robustness to temperature and voltage variations (
$-$
40
$^\circ$
C to 105
$^{\circ}$
C and 0.65 to 1.2 V) among SRAM-based analog CIM designs.