A Generic Multidimensional Design Methodology for Highly Efficient RF Power Amplifier with Improved Linearity

This article presents a generic multidimensional design methodology for power amplifiers (PAs) with enhanced linearity and efficiency. The proposed design is composed of in-phase parallel PA configurations with optimized different gate biases. The coefficients of the fundamental and harmonic currents are analyzed and studied for FET transistors considering the variation of input power and conduction angle. This analysis added an extra degree of freedom in PA design and enabled PA performance enhancement over a wider range of output power levels not only at maximum points. This helps optimize the bias point of each PA to provide either a highly efficient PA with the best achievable linearity or a highly linear PA with the best achievable efficiency. A visualized transistor datasets and a novel algorithm are developed to select the optimum gate bias voltages over a wide input power range to optimize the parallel configuration’s efficiency and linearity. To verify the proposed methodology, a 20-W highly efficient PA with the best achievable linearity is designed, fabricated, and measured at a center frequency of 2.2 GHz with a bandwidth of 200 MHz. Very good agreement is achieved between simulation and measurement results. The measured results showed good linearity with IM3 up to −55 dBc at 10 dB output power back-off (OBO). The 1 dB compression point is achieved at 43 dBm output power, while the saturated output power (
$P_{\mathrm {sat}}$
) is 43.6 dBm at a measured power-added efficiency (PAE) of 68%. Good linearity measurements are achieved with adjacent channel power ratio (ACPR) of −29 dBc at an average output power of 41.6 dBm and an average PAE of more than 47%. The error vector magnitude (EVM) is less than 2.4% at the average output power.