A Symmetric Bridge-Based Pre-Bond TSV Faults Detection Method

Three-dimensional integrated circuits (3-D ICs) based on through-silicon via (TSV) have helped to improve the transistor density and are considered as an important technology supporting Moore’s law. Pre-bond TSV test can effectively improve the performance and yield of 3-D ICs. This article proposes a symmetric bridge technique for the pre-bond TSV test. The proposed method treats the TSV as a capacitor placed on the bridge arm and enables the elements in the adjacent bridge arms to be symmetric and equal. When TSV is fault-free, the peak voltages at the two points diagonally across the bridge are equal; when TSV has a full-open fault, partial-open fault, or leakage fault, the peak voltages at the two points are no longer equal. A peak detection circuit is presented to detect the peak voltages and distinguish the fault types of TSV. Finally, a serial test architecture is presented to reduce the hardware overhead. Experiment results show that the proposed technique has better fault detection capability and better robustness against process, voltage, and temperature (PVT) variations compared to the ac bridge method.