Contents I. Introduction
The recent trend in active-matrix organic light-emitting diode (AMOLED) displays for mobile devices has focused on the realization of higher resolution and brightness, along with low power consumption. Owing to the benefits of longer device operation and extended battery life, decreasing power consumption has become a crucial aspect of modern display technology development. The most common approach for reducing power consumption involves lowering the driving frequency to decrease power consumption during on/off transitions [1]. Amorphous indium-gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) possess remarkably low off-current characteristics, which prevents the degradation of display quality, such as color shifts or flickering, even at reduced frame rates. Consequently, low-temperature polycrystalline silicon and oxide (LTPO) TFT backplane technology, which combines a-IGZO TFTs with the superior electrical properties of low-temperature polysilicon TFTs (LTPS-TFTs), has recently attracted significant attention [2]. However, the LTPO TFT fabrication process is highly complex because it requires sequential production of two different types of TFTs. The manufacturing process can be simplified by enhancing the electrical properties of oxide TFTs, which are currently being studied as alternatives to LTPS. Various approaches have been studied to improve the electrical properties of a-IGZO TFTs, including modifying the gate insulator (GI) material, treating the oxide-GI interface, and changing the doping conditions [3], [4], [5]. One simple method involves enhancing the electrical characteristics by applying a double-gate (DG) structure [6], [7]. This structure improves the switching capability and on-current characteristics of TFTs by applying a gate voltage to both sides of the a-IGZO channel, thereby utilizing the two channels. In addition, the DG metal blocks the incident light on the a-IGZO TFT, thereby preventing the formation of ionized oxygen vacancies and generating holes at the GI interface, which can improve the negative bias temperature illumination stress (NBTIS) performance [8]. Moreover, the bottom gate (BG) of the DG structure can shield the impact of mobile charges within the polyimide (PI) used in flexible displays, contributing to the improvement in the reliability characteristics of TFTs or enhancing the image retention performance during display operation [9], [10]. The voltage applied to the top/BG of the DG a-IGZO TFTs is a key factor in determining the characteristics. Previous studies on DG structures have primarily focused on adjusting the subgate voltage separately from the main gate voltage to control the threshold voltage (). Other studies have attempted to synchronize it with the main gate to enhance the electrical characteristics [11]. However, a broader set of factors should be considered for the application of DG a-IGZO TFTs. Specifically, for AMOLED display applications, the performance of TFT devices must be optimized to ensure superior image quality. AMOLED displays incorporate pixel compensation circuits to minimize image quality degradation caused by TFT variations. These compensation circuits comprise driving TFTs (), which apply current to the OLED, and switching TFTs (), which are responsible for luminance adjustment and compensation of variations [12]. Maximizing the compensation performance is necessary to prevent image-quality degradation caused by variations within the compensation pixels. In particular, the subthreshold swing (SS) characteristics of can enhance the sensitivity of the OLED current to gate voltage () fluctuations. Therefore, increasing the SS, even if there is a slight decrease in the electrical properties, is advantageous for image quality characteristics. In this study, a DG structure was fabricated by adding a BG to a top-gate coplanar a-IGZO TFT, and its TFT characteristics were investigated. The voltage applied to the fabricated BG was synchronized with either the source node or the top gate to investigate the electrical characteristic variations according to the different modes. Furthermore, methods for optimizing the compensation performance were explored through the application of BG connection modes to four nMOS TFTs and two capacitor (4T2C) circuits [13].
