A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip

In the past, a small size microcontroller was needed to control and gather data from resource-constrained electronic devices aimed at Internet of Things (IoT) applications. While the server nodes receive the requests with a high demand for calculation. However, to minimize network traffic transactions and the overall workload that the server node must handle, a portion of these operations must now be completed locally. Additionally, multiple tasks must be processed simultaneously by IoT devices. In this study, we suggested a multi-core, multi-thread enable System-on-Chip (SoC) that consume small resources. The suggested architecture achieves a notable speed increase over single-core design by utilizing the advantages of RISC-V Instruction Set Architecture (ISA).