System-level design for DPCM Image Compression with SoC-FPGA Accelerator

The implementation of data compression in embedded platforms and portable systems is growing rapidly due to the demands for image and video processing in daily human life. Among the data compression applications, medical imaging, such as Computed Tomography (CT), and Light Detection And Ranging (LiDAR) have become active research areas, especially when data transmissions must be performed over a communication interface.Because of the complexity of data compression algorithms and the high resolution of input streams, current embedded platforms may not be able to fully exploit data compression algorithms. To address this restriction, recent approaches utilize hardware accelerators to speed up the computation. Among available hardware accelerators, system-on-a-chip field-programmable gate arrays (SoC-FPGAs) have emerged as an important architecture approach in terms of achieving satisfactory computational performances. This study presents a hardware accelerator for the computation of a differential pulse code modulation (DPCM) algorithm implemented and synthesized on a Zynq SoC-FPGA and achieving an acceleration factor of 88x.