Quality Compliance of HDI PCBs for Space Use

Increasing micro-miniaturisation is driving decrease in volume of electronic packages, putting stringent demand on use of cutting-edge ultra-high density I/O devices in smaller real estate on PCBs. This has put emphasis on PCB technologies like HDI that uses micro-vias as interconnects. It employs sequential build, unlike conventional MLBs, with blind & buried micro-vias on the outer-most layers along with buried vias in inner-layers. This in-turn provides increased circuit density in the PCB and are compatible with the latest high-density IC packaging technologies. This paper covers critical quality evaluation methodology to assess the space worthiness of HDI technology and its outcomes.

I. INTRODUCTION

The conventional PCBs can have a better real-estate optimization if the through hole vertical interconnect access (via) and its mandatory keep-off zone can be mitigated. This objective is met by HDI (High Density Interconnect) PCBs, providing the necessary support to micro-miniaturization demands. HDI contains fine line & spacing of ≤100µm along with buried, blind & micro-vias. IPC standards [1] define microvias as blind or buried vias with a diameter ≤150μm. The advancement in miniaturization of the electronic devices has led to the development of micro-vias from single level structure to stacked & staggered type configuration. Both types of micro-vias are generally filled using electrodeposited copper for making electrical connections among the different conductor layers and also to provide structural support to the outer micro-vias & components mounted on outer pads of the PCB.