Load balancing-oriented fault-tolerant NoC design

Network-on-Chip (NoC) has been widely applied in modern chip multiprocessors due to its high bandwidth and scalability. However, as technology advances to the nanometer scale, NoC is increasingly vulnerable to errors caused by crosstalk, radiation, electromagnetic interference, etc. Conventional Switch-to-Switch (S2S) fault-tolerant designs based on ECC have overlooked the characteristic of the distribution of traffic load. This oversight not only increases area overhead significantly but also leads to low average utilization of ECC decoder modules. In this paper, we analyze the distribution of traffic load in mesh network and propose a load balancing-oriented fault-tolerant NoC design. The core idea is to allocate different numbers of ECC decoder modules to each router based on the distribution of traffic load, aiming to improve the average utilization of ECC decoder modules and reduce the area overhead without compromising fault-tolerant capability of NoC. The experiment under 6 common synthetic traffic patterns shows that compared to the baseline, our design exhibits an average delay performance loss of less than 0.88%. Additionally, the maximum reduction in the number of ECC decoder modules is 160, the maximum reduction in the area overhead of NoC is 15.06%, and the maximum improvement in the average utilization of ECC decoder modules is 1.21x. Furthermore, the experiment under PARSEC benchmarks shows that compared to the baseline, our design exhibits an average delay performance loss of less than 0.08%. Additionally, the maximum reduction in the number of ECC decoder modules is 156, the maximum reduction in total NoC area overhead is 14.69%, and the maximum improvement in the average utilization of ECC decoder modules is 1.13x.