Analysis of Optimization on Sparse Matrix Vector Multiplication Model Application in Digital Signal Processing

Conventional digital signal processing (DSP) technology, utilizing DSP and FPGA, excels in real-time signal processing but faces limitations in handling large-scale data and achieving high frequency resolution. This restricts its effectiveness for tasks involving offline data processing, analysis, and mining in applications with extensive data volumes. Some of the SpMV applications in image editing operations like linear filtering, resizing and mixing are reformulated in the SpMV multiplication form. The growing complexity of applications and the demand for top-notch digital data necessitate a boost in processing power. With energy efficiency becoming a critical concern, there is research on designing SpMV algorithms that minimize energy consumption. This is particularly relevant for embedded DSP systems and applications where power efficiency is a key consideration. A comparative study of High-Level Synthesis (HLS) techniques to reduce the power consumption and resource utilization conducted on Xilinx-Zynq 7000 FPGA is presented. This paper explores various HLS pragmas techniques using OpenCL framework applied on Sparse Matrix Vector Multiplication (SpMV) kernel for optimizing power efficiency and resource utilization. HLS has emerged has a pivotal technology for simplifying the design process of complex digital systems by allowing developers to work at higher levels of abstraction, using high-level programming languages. From the analysis, identified the best optimization technique for the low power and the minimum resource utilization for the SpMV implementation on FPGA hence it can be more useful for applications in the field of CNN.