Implementation of High-Speed Multi-Trit Adders for Balanced and Unbalanced Ternary Logic

Ternary logic with larger data density has great potential in high-performance data processing. Even though ternary half/full adders have been intensively investigated in recent years, the high-speed multi-trit ternary adders, which are urgently needed for high-efficient ternary computing, remain unexplored. In this study, we present ternary carry lookahead adders (CLAs) to eliminate the tedious delay caused by the cascade-connected carry signals. Different implementation methods are used for unbalanced and balanced ternary logic. A delay analysis model of ternary CLAs is established. Compared with reported ternary carry ripple adders (CRAs), our 5-trit unbalanced and balanced ternary CLAs can achieve a 61.45% and 75.18% reduction in delay, respectively.